lat_mem_rd.py revision 11656
111656Sandreas.hansson@arm.com# Copyright (c) 2015-2016 ARM Limited 211368Sandreas.hansson@arm.com# All rights reserved. 311368Sandreas.hansson@arm.com# 411368Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 511368Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 611368Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 711368Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 811368Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 911368Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 1011368Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 1111368Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 1211368Sandreas.hansson@arm.com# 1311368Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 1411368Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 1511368Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 1611368Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 1711368Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 1811368Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 1911368Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 2011368Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 2111368Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 2211368Sandreas.hansson@arm.com# this software without specific prior written permission. 2311368Sandreas.hansson@arm.com# 2411368Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2511368Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2611368Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2711368Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2811368Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2911368Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3011368Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3111368Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3211368Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3311368Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3411368Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3511368Sandreas.hansson@arm.com# 3611368Sandreas.hansson@arm.com# Authors: Andreas Hansson 3711368Sandreas.hansson@arm.com 3811368Sandreas.hansson@arm.comimport gzip 3911368Sandreas.hansson@arm.comimport optparse 4011368Sandreas.hansson@arm.comimport os 4111368Sandreas.hansson@arm.com 4211368Sandreas.hansson@arm.comimport m5 4311368Sandreas.hansson@arm.comfrom m5.objects import * 4411368Sandreas.hansson@arm.comfrom m5.util import addToPath 4511368Sandreas.hansson@arm.comfrom m5.internal.stats import periodicStatDump 4611368Sandreas.hansson@arm.com 4711368Sandreas.hansson@arm.comaddToPath('../common') 4811368Sandreas.hansson@arm.comimport MemConfig 4911368Sandreas.hansson@arm.com 5011368Sandreas.hansson@arm.comaddToPath('../../util') 5111368Sandreas.hansson@arm.comimport protolib 5211368Sandreas.hansson@arm.com 5311368Sandreas.hansson@arm.com# this script is helpful to observe the memory latency for various 5411368Sandreas.hansson@arm.com# levels in a cache hierarchy, and various cache and memory 5511368Sandreas.hansson@arm.com# configurations, in essence replicating the lmbench lat_mem_rd thrash 5611368Sandreas.hansson@arm.com# behaviour 5711368Sandreas.hansson@arm.com 5811368Sandreas.hansson@arm.com# import the packet proto definitions, and if they are not found, 5911368Sandreas.hansson@arm.com# attempt to generate them automatically 6011368Sandreas.hansson@arm.comtry: 6111368Sandreas.hansson@arm.com import packet_pb2 6211368Sandreas.hansson@arm.comexcept: 6311368Sandreas.hansson@arm.com print "Did not find packet proto definitions, attempting to generate" 6411368Sandreas.hansson@arm.com from subprocess import call 6511368Sandreas.hansson@arm.com error = call(['protoc', '--python_out=configs/dram', 6611368Sandreas.hansson@arm.com '--proto_path=src/proto', 'src/proto/packet.proto']) 6711368Sandreas.hansson@arm.com if not error: 6811368Sandreas.hansson@arm.com print "Generated packet proto definitions" 6911368Sandreas.hansson@arm.com 7011368Sandreas.hansson@arm.com try: 7111368Sandreas.hansson@arm.com import google.protobuf 7211368Sandreas.hansson@arm.com except: 7311368Sandreas.hansson@arm.com print "Please install the Python protobuf module" 7411368Sandreas.hansson@arm.com exit(-1) 7511368Sandreas.hansson@arm.com 7611368Sandreas.hansson@arm.com import packet_pb2 7711368Sandreas.hansson@arm.com else: 7811368Sandreas.hansson@arm.com print "Failed to import packet proto definitions" 7911368Sandreas.hansson@arm.com exit(-1) 8011368Sandreas.hansson@arm.com 8111368Sandreas.hansson@arm.comparser = optparse.OptionParser() 8211368Sandreas.hansson@arm.com 8311368Sandreas.hansson@arm.comparser.add_option("--mem-type", type="choice", default="DDR3_1600_x64", 8411368Sandreas.hansson@arm.com choices=MemConfig.mem_names(), 8511368Sandreas.hansson@arm.com help = "type of memory to use") 8611368Sandreas.hansson@arm.comparser.add_option("--mem-size", action="store", type="string", 8711368Sandreas.hansson@arm.com default="16MB", 8811368Sandreas.hansson@arm.com help="Specify the memory size") 8911368Sandreas.hansson@arm.comparser.add_option("--reuse-trace", action="store_true", 9011368Sandreas.hansson@arm.com help="Prevent generation of traces and reuse existing") 9111368Sandreas.hansson@arm.com 9211368Sandreas.hansson@arm.com(options, args) = parser.parse_args() 9311368Sandreas.hansson@arm.com 9411368Sandreas.hansson@arm.comif args: 9511368Sandreas.hansson@arm.com print "Error: script doesn't take any positional arguments" 9611368Sandreas.hansson@arm.com sys.exit(1) 9711368Sandreas.hansson@arm.com 9811368Sandreas.hansson@arm.com# start by creating the system itself, using a multi-layer 2.0 GHz 9911368Sandreas.hansson@arm.com# crossbar, delivering 64 bytes / 3 cycles (one header cycle) which 10011368Sandreas.hansson@arm.com# amounts to 42.7 GByte/s per layer and thus per port 10111368Sandreas.hansson@arm.comsystem = System(membus = SystemXBar(width = 32)) 10211368Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = '2.0GHz', 10311368Sandreas.hansson@arm.com voltage_domain = 10411368Sandreas.hansson@arm.com VoltageDomain(voltage = '1V')) 10511368Sandreas.hansson@arm.com 10611368Sandreas.hansson@arm.commem_range = AddrRange(options.mem_size) 10711368Sandreas.hansson@arm.comsystem.mem_ranges = [mem_range] 10811368Sandreas.hansson@arm.com 10911368Sandreas.hansson@arm.com# do not worry about reserving space for the backing store 11011368Sandreas.hansson@arm.comsystem.mmap_using_noreserve = True 11111368Sandreas.hansson@arm.com 11211368Sandreas.hansson@arm.com# currently not exposed as command-line options, set here for now 11311368Sandreas.hansson@arm.comoptions.mem_channels = 1 11411368Sandreas.hansson@arm.comoptions.mem_ranks = 1 11511368Sandreas.hansson@arm.comoptions.external_memory_system = 0 11611368Sandreas.hansson@arm.comoptions.tlm_memory = 0 11711368Sandreas.hansson@arm.comoptions.elastic_trace_en = 0 11811368Sandreas.hansson@arm.com 11911368Sandreas.hansson@arm.comMemConfig.config_mem(options, system) 12011368Sandreas.hansson@arm.com 12111368Sandreas.hansson@arm.com# there is no point slowing things down by saving any data 12211368Sandreas.hansson@arm.comfor ctrl in system.mem_ctrls: 12311368Sandreas.hansson@arm.com ctrl.null = True 12411368Sandreas.hansson@arm.com 12511368Sandreas.hansson@arm.com # the following assumes that we are using the native DRAM 12611368Sandreas.hansson@arm.com # controller, check to be sure 12711368Sandreas.hansson@arm.com if isinstance(ctrl, m5.objects.DRAMCtrl): 12811368Sandreas.hansson@arm.com # make the DRAM refresh interval sufficiently infinite to avoid 12911368Sandreas.hansson@arm.com # latency spikes 13011368Sandreas.hansson@arm.com ctrl.tREFI = '100s' 13111368Sandreas.hansson@arm.com 13211368Sandreas.hansson@arm.com# use the same concept as the utilisation sweep, and print the config 13311368Sandreas.hansson@arm.com# so that we can later read it in 13411368Sandreas.hansson@arm.comcfg_file_name = os.path.join(m5.options.outdir, "lat_mem_rd.cfg") 13511368Sandreas.hansson@arm.comcfg_file = open(cfg_file_name, 'w') 13611368Sandreas.hansson@arm.com 13711368Sandreas.hansson@arm.com# set an appropriate burst length in bytes 13811368Sandreas.hansson@arm.comburst_size = 64 13911368Sandreas.hansson@arm.comsystem.cache_line_size = burst_size 14011368Sandreas.hansson@arm.com 14111368Sandreas.hansson@arm.com# lazy version to check if an integer is a power of two 14211368Sandreas.hansson@arm.comdef is_pow2(num): 14311368Sandreas.hansson@arm.com return num != 0 and ((num & (num - 1)) == 0) 14411368Sandreas.hansson@arm.com 14511368Sandreas.hansson@arm.com# assume we start every range at 0 14611368Sandreas.hansson@arm.commax_range = int(mem_range.end) 14711368Sandreas.hansson@arm.com 14811368Sandreas.hansson@arm.com# start at a size of 4 kByte, and go up till we hit the max, increase 14911368Sandreas.hansson@arm.com# the step every time we hit a power of two 15011368Sandreas.hansson@arm.commin_range = 4096 15111368Sandreas.hansson@arm.comranges = [min_range] 15211368Sandreas.hansson@arm.comstep = 1024 15311368Sandreas.hansson@arm.com 15411368Sandreas.hansson@arm.comwhile ranges[-1] < max_range: 15511368Sandreas.hansson@arm.com new_range = ranges[-1] + step 15611368Sandreas.hansson@arm.com if is_pow2(new_range): 15711368Sandreas.hansson@arm.com step *= 2 15811368Sandreas.hansson@arm.com ranges.append(new_range) 15911368Sandreas.hansson@arm.com 16011368Sandreas.hansson@arm.com# how many times to repeat the measurement for each data point 16111368Sandreas.hansson@arm.comiterations = 2 16211368Sandreas.hansson@arm.com 16311368Sandreas.hansson@arm.com# 150 ns in ticks, this is choosen to be high enough that transactions 16411368Sandreas.hansson@arm.com# do not pile up in the system, adjust if needed 16511368Sandreas.hansson@arm.comitt = 150 * 1000 16611368Sandreas.hansson@arm.com 16711368Sandreas.hansson@arm.com# for every data point, we create a trace containing a random address 16811368Sandreas.hansson@arm.com# sequence, so that we can play back the same sequence for warming and 16911368Sandreas.hansson@arm.com# the actual measurement 17011368Sandreas.hansson@arm.comdef create_trace(filename, max_addr, burst_size, itt): 17111368Sandreas.hansson@arm.com try: 17211368Sandreas.hansson@arm.com proto_out = gzip.open(filename, 'wb') 17311368Sandreas.hansson@arm.com except IOError: 17411368Sandreas.hansson@arm.com print "Failed to open ", filename, " for writing" 17511368Sandreas.hansson@arm.com exit(-1) 17611368Sandreas.hansson@arm.com 17711368Sandreas.hansson@arm.com # write the magic number in 4-byte Little Endian, similar to what 17811368Sandreas.hansson@arm.com # is done in src/proto/protoio.cc 17911368Sandreas.hansson@arm.com proto_out.write("gem5") 18011368Sandreas.hansson@arm.com 18111368Sandreas.hansson@arm.com # add the packet header 18211368Sandreas.hansson@arm.com header = packet_pb2.PacketHeader() 18311368Sandreas.hansson@arm.com header.obj_id = "lat_mem_rd for range 0:" + str(max_addr) 18411368Sandreas.hansson@arm.com # assume the default tick rate (1 ps) 18511368Sandreas.hansson@arm.com header.tick_freq = 1000000000000 18611368Sandreas.hansson@arm.com protolib.encodeMessage(proto_out, header) 18711368Sandreas.hansson@arm.com 18811368Sandreas.hansson@arm.com # create a list of every single address to touch 18911368Sandreas.hansson@arm.com addrs = range(0, max_addr, burst_size) 19011368Sandreas.hansson@arm.com 19111368Sandreas.hansson@arm.com import random 19211368Sandreas.hansson@arm.com random.shuffle(addrs) 19311368Sandreas.hansson@arm.com 19411368Sandreas.hansson@arm.com tick = 0 19511368Sandreas.hansson@arm.com 19611368Sandreas.hansson@arm.com # create a packet we can re-use for all the addresses 19711368Sandreas.hansson@arm.com packet = packet_pb2.Packet() 19811368Sandreas.hansson@arm.com # ReadReq is 1 in src/mem/packet.hh Command enum 19911368Sandreas.hansson@arm.com packet.cmd = 1 20011368Sandreas.hansson@arm.com packet.size = int(burst_size) 20111368Sandreas.hansson@arm.com 20211368Sandreas.hansson@arm.com for addr in addrs: 20311368Sandreas.hansson@arm.com packet.tick = long(tick) 20411368Sandreas.hansson@arm.com packet.addr = long(addr) 20511368Sandreas.hansson@arm.com protolib.encodeMessage(proto_out, packet) 20611368Sandreas.hansson@arm.com tick = tick + itt 20711368Sandreas.hansson@arm.com 20811368Sandreas.hansson@arm.com proto_out.close() 20911368Sandreas.hansson@arm.com 21011368Sandreas.hansson@arm.com# this will take a while, so keep the user informed 21111368Sandreas.hansson@arm.comprint "Generating traces, please wait..." 21211368Sandreas.hansson@arm.com 21311368Sandreas.hansson@arm.comnxt_range = 0 21411368Sandreas.hansson@arm.comnxt_state = 0 21511368Sandreas.hansson@arm.comperiod = long(itt * (max_range / burst_size)) 21611368Sandreas.hansson@arm.com 21711368Sandreas.hansson@arm.com# now we create the states for each range 21811368Sandreas.hansson@arm.comfor r in ranges: 21911368Sandreas.hansson@arm.com filename = os.path.join(m5.options.outdir, 22011368Sandreas.hansson@arm.com 'lat_mem_rd%d.trc.gz' % nxt_range) 22111368Sandreas.hansson@arm.com 22211368Sandreas.hansson@arm.com if not options.reuse_trace: 22311368Sandreas.hansson@arm.com # create the actual random trace for this range 22411368Sandreas.hansson@arm.com create_trace(filename, r, burst_size, itt) 22511368Sandreas.hansson@arm.com 22611368Sandreas.hansson@arm.com # the warming state 22711368Sandreas.hansson@arm.com cfg_file.write("STATE %d %d TRACE %s 0\n" % 22811368Sandreas.hansson@arm.com (nxt_state, period, filename)) 22911368Sandreas.hansson@arm.com nxt_state = nxt_state + 1 23011368Sandreas.hansson@arm.com 23111368Sandreas.hansson@arm.com # the measuring states 23211368Sandreas.hansson@arm.com for i in range(iterations): 23311368Sandreas.hansson@arm.com cfg_file.write("STATE %d %d TRACE %s 0\n" % 23411368Sandreas.hansson@arm.com (nxt_state, period, filename)) 23511368Sandreas.hansson@arm.com nxt_state = nxt_state + 1 23611368Sandreas.hansson@arm.com 23711368Sandreas.hansson@arm.com nxt_range = nxt_range + 1 23811368Sandreas.hansson@arm.com 23911368Sandreas.hansson@arm.comcfg_file.write("INIT 0\n") 24011368Sandreas.hansson@arm.com 24111368Sandreas.hansson@arm.com# go through the states one by one 24211368Sandreas.hansson@arm.comfor state in range(1, nxt_state): 24311368Sandreas.hansson@arm.com cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state)) 24411368Sandreas.hansson@arm.com 24511368Sandreas.hansson@arm.comcfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1)) 24611368Sandreas.hansson@arm.com 24711368Sandreas.hansson@arm.comcfg_file.close() 24811368Sandreas.hansson@arm.com 24911368Sandreas.hansson@arm.com# create a traffic generator, and point it to the file we just created 25011656Sandreas.hansson@arm.comsystem.tgen = TrafficGen(config_file = cfg_file_name, 25111656Sandreas.hansson@arm.com progress_check = '10s') 25211368Sandreas.hansson@arm.com 25311368Sandreas.hansson@arm.com# add a communication monitor 25411368Sandreas.hansson@arm.comsystem.monitor = CommMonitor() 25511368Sandreas.hansson@arm.com 25611368Sandreas.hansson@arm.com# connect the traffic generator to the system 25711368Sandreas.hansson@arm.comsystem.tgen.port = system.monitor.slave 25811368Sandreas.hansson@arm.com 25911368Sandreas.hansson@arm.com# create the actual cache hierarchy, for now just go with something 26011368Sandreas.hansson@arm.com# basic to explore some of the options 26111368Sandreas.hansson@arm.comfrom Caches import * 26211368Sandreas.hansson@arm.com 26311368Sandreas.hansson@arm.com# a starting point for an L3 cache 26411368Sandreas.hansson@arm.comclass L3Cache(Cache): 26511368Sandreas.hansson@arm.com assoc = 16 26611368Sandreas.hansson@arm.com hit_latency = 40 26711368Sandreas.hansson@arm.com response_latency = 40 26811368Sandreas.hansson@arm.com mshrs = 32 26911368Sandreas.hansson@arm.com tgts_per_mshr = 12 27011368Sandreas.hansson@arm.com write_buffers = 16 27111368Sandreas.hansson@arm.com 27211368Sandreas.hansson@arm.com# note that everything is in the same clock domain, 2.0 GHz as 27311368Sandreas.hansson@arm.com# specified above 27411368Sandreas.hansson@arm.comsystem.l1cache = L1_DCache(size = '64kB') 27511368Sandreas.hansson@arm.comsystem.monitor.master = system.l1cache.cpu_side 27611368Sandreas.hansson@arm.com 27711368Sandreas.hansson@arm.comsystem.l2cache = L2Cache(size = '512kB', writeback_clean = True) 27811368Sandreas.hansson@arm.comsystem.l2cache.xbar = L2XBar() 27911368Sandreas.hansson@arm.comsystem.l1cache.mem_side = system.l2cache.xbar.slave 28011368Sandreas.hansson@arm.comsystem.l2cache.cpu_side = system.l2cache.xbar.master 28111368Sandreas.hansson@arm.com 28211368Sandreas.hansson@arm.com# make the L3 mostly exclusive, and correspondingly ensure that the L2 28311368Sandreas.hansson@arm.com# writes back also clean lines to the L3 28411368Sandreas.hansson@arm.comsystem.l3cache = L3Cache(size = '4MB', clusivity = 'mostly_excl') 28511368Sandreas.hansson@arm.comsystem.l3cache.xbar = L2XBar() 28611368Sandreas.hansson@arm.comsystem.l2cache.mem_side = system.l3cache.xbar.slave 28711368Sandreas.hansson@arm.comsystem.l3cache.cpu_side = system.l3cache.xbar.master 28811368Sandreas.hansson@arm.comsystem.l3cache.mem_side = system.membus.slave 28911368Sandreas.hansson@arm.com 29011368Sandreas.hansson@arm.com# connect the system port even if it is not used in this example 29111368Sandreas.hansson@arm.comsystem.system_port = system.membus.slave 29211368Sandreas.hansson@arm.com 29311368Sandreas.hansson@arm.com# every period, dump and reset all stats 29411368Sandreas.hansson@arm.comperiodicStatDump(period) 29511368Sandreas.hansson@arm.com 29611368Sandreas.hansson@arm.com# run Forrest, run! 29711368Sandreas.hansson@arm.comroot = Root(full_system = False, system = system) 29811368Sandreas.hansson@arm.comroot.system.mem_mode = 'timing' 29911368Sandreas.hansson@arm.com 30011368Sandreas.hansson@arm.comm5.instantiate() 30111368Sandreas.hansson@arm.comm5.simulate(nxt_state * period) 30211368Sandreas.hansson@arm.com 30311368Sandreas.hansson@arm.com# print all we need to make sense of the stats output 30411368Sandreas.hansson@arm.comprint "lat_mem_rd with %d iterations, ranges:" % iterations 30511368Sandreas.hansson@arm.comfor r in ranges: 30611368Sandreas.hansson@arm.com print r 307