sw.py revision 11844:d229654ff4c2
19243SN/A# Copyright (c) 2015 The University of Illinois Urbana Champaign 210206Sandreas.hansson@arm.com# All rights reserved 39243SN/A# 49243SN/A# Redistribution and use in source and binary forms, with or without 59243SN/A# modification, are permitted provided that the following conditions are 69243SN/A# met: redistributions of source code must retain the above copyright 79243SN/A# notice, this list of conditions and the following disclaimer; 89243SN/A# redistributions in binary form must reproduce the above copyright 99243SN/A# notice, this list of conditions and the following disclaimer in the 109243SN/A# documentation and/or other materials provided with the distribution; 119243SN/A# neither the name of the copyright holders nor the names of its 129243SN/A# contributors may be used to endorse or promote products derived from 139243SN/A# this software without specific prior written permission. 149831SN/A# 159831SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 169831SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 179243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 189243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 199243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 209243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 219243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 229243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 239243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 249243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 259243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 269243SN/A# 279243SN/A# Authors: Mohammad Alian 289243SN/A 299243SN/A# This is an example of an n port network switch to work in dist-gem5. 309243SN/A# Users can extend this to have different different topologies 319243SN/A 329243SN/Aimport optparse 339243SN/Aimport sys 349243SN/A 359243SN/Aimport m5 369243SN/Afrom m5.defines import buildEnv 379243SN/Afrom m5.objects import * 389243SN/Afrom m5.util import addToPath, fatal 399243SN/A 409243SN/AaddToPath('../') 419243SN/A 429967SN/Afrom common import Simulation 439243SN/Afrom common import Options 449243SN/A 459243SN/Adef build_switch(options): 469243SN/A # instantiate an EtherSwitch 4710146Sandreas.hansson@arm.com switch = EtherSwitch() 489243SN/A # instantiate distEtherLinks to connect switch ports 499243SN/A # to other gem5 instances 5010146Sandreas.hansson@arm.com switch.portlink = [DistEtherLink(speed = options.ethernet_linkspeed, 5110146Sandreas.hansson@arm.com delay = options.ethernet_linkdelay, 529243SN/A dist_rank = options.dist_rank, 539488SN/A dist_size = options.dist_size, 549488SN/A server_name = options.dist_server_name, 559243SN/A server_port = options.dist_server_port, 569243SN/A sync_start = options.dist_sync_start, 579243SN/A sync_repeat = options.dist_sync_repeat, 589243SN/A is_switch = True, 599243SN/A num_nodes = options.dist_size) 609243SN/A for i in xrange(options.dist_size)] 6110146Sandreas.hansson@arm.com 629243SN/A for (i, link) in enumerate(switch.portlink): 639243SN/A link.int0 = switch.interface[i] 649243SN/A 6510146Sandreas.hansson@arm.com return switch 6610146Sandreas.hansson@arm.com 6710146Sandreas.hansson@arm.comdef main(): 689243SN/A # Add options 699243SN/A parser = optparse.OptionParser() 709243SN/A Options.addCommonOptions(parser) 719243SN/A Options.addFSOptions(parser) 729243SN/A (options, args) = parser.parse_args() 739243SN/A 749243SN/A system = build_switch(options) 759243SN/A root = Root(full_system = True, system = system) 769243SN/A Simulation.run(options, root, None, None) 779243SN/A 789243SN/Aif __name__ == "__m5_main__": 799243SN/A main() 809243SN/A