ex5_LITTLE.py revision 12600:e670dd17c8cf
17119Sgblack@eecs.umich.edu# Copyright (c) 2012 The Regents of The University of Michigan
27119Sgblack@eecs.umich.edu# Copyright (c) 2016 Centre National de la Recherche Scientifique
37119Sgblack@eecs.umich.edu# All rights reserved.
47119Sgblack@eecs.umich.edu#
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77119Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright
87119Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
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147119Sgblack@eecs.umich.edu# this software without specific prior written permission.
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277119Sgblack@eecs.umich.edu#
287119Sgblack@eecs.umich.edu# Authors: Ron Dreslinski
297119Sgblack@eecs.umich.edu#          Anastasiia Butko
307119Sgblack@eecs.umich.edu#          Louisa Bessad
317119Sgblack@eecs.umich.edu
327119Sgblack@eecs.umich.edufrom m5.objects import *
337119Sgblack@eecs.umich.edu
347119Sgblack@eecs.umich.edu#-----------------------------------------------------------------------
357119Sgblack@eecs.umich.edu#                ex5 LITTLE core (based on the ARM Cortex-A7)
367119Sgblack@eecs.umich.edu#-----------------------------------------------------------------------
377119Sgblack@eecs.umich.edu
387119Sgblack@eecs.umich.edu# Simple ALU Instructions have a latency of 3
397119Sgblack@eecs.umich.educlass ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
407119Sgblack@eecs.umich.edu    opList = [ OpDesc(opClass='IntAlu', opLat=4) ]
417119Sgblack@eecs.umich.edu
427119Sgblack@eecs.umich.edu# Complex ALU instructions have a variable latencies
437119Sgblack@eecs.umich.educlass ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU):
447119Sgblack@eecs.umich.edu    opList = [ OpDesc(opClass='IntMult', opLat=7) ]
457119Sgblack@eecs.umich.edu
467119Sgblack@eecs.umich.educlass ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU):
477119Sgblack@eecs.umich.edu    opList = [ OpDesc(opClass='IntDiv', opLat=9) ]
487119Sgblack@eecs.umich.edu
497119Sgblack@eecs.umich.edu# Floating point and SIMD instructions
507119Sgblack@eecs.umich.educlass ex5_LITTLE_FP(MinorDefaultFloatSimdFU):
517119Sgblack@eecs.umich.edu    opList = [ OpDesc(opClass='SimdAdd', opLat=6),
527119Sgblack@eecs.umich.edu               OpDesc(opClass='SimdAddAcc', opLat=4),
537119Sgblack@eecs.umich.edu               OpDesc(opClass='SimdAlu', opLat=4),
547119Sgblack@eecs.umich.edu               OpDesc(opClass='SimdCmp', opLat=1),
557119Sgblack@eecs.umich.edu               OpDesc(opClass='SimdCvt', opLat=3),
567128Sgblack@eecs.umich.edu               OpDesc(opClass='SimdMisc', opLat=3),
577128Sgblack@eecs.umich.edu               OpDesc(opClass='SimdMult',opLat=4),
587128Sgblack@eecs.umich.edu               OpDesc(opClass='SimdMultAcc',opLat=5),
597128Sgblack@eecs.umich.edu               OpDesc(opClass='SimdShift',opLat=3),
607128Sgblack@eecs.umich.edu               OpDesc(opClass='SimdShiftAcc', opLat=3),
617128Sgblack@eecs.umich.edu               OpDesc(opClass='SimdSqrt', opLat=9),
627279Sgblack@eecs.umich.edu               OpDesc(opClass='SimdFloatAdd',opLat=8),
637279Sgblack@eecs.umich.edu               OpDesc(opClass='SimdFloatAlu',opLat=6),
647119Sgblack@eecs.umich.edu               OpDesc(opClass='SimdFloatCmp', opLat=6),
657119Sgblack@eecs.umich.edu               OpDesc(opClass='SimdFloatCvt', opLat=6),
667119Sgblack@eecs.umich.edu               OpDesc(opClass='SimdFloatDiv', opLat=20, pipelined=False),
677119Sgblack@eecs.umich.edu               OpDesc(opClass='SimdFloatMisc', opLat=6),
687132Sgblack@eecs.umich.edu               OpDesc(opClass='SimdFloatMult', opLat=15),
697303Sgblack@eecs.umich.edu               OpDesc(opClass='SimdFloatMultAcc',opLat=6),
707303Sgblack@eecs.umich.edu               OpDesc(opClass='SimdFloatSqrt', opLat=17),
717132Sgblack@eecs.umich.edu               OpDesc(opClass='FloatAdd', opLat=8),
727119Sgblack@eecs.umich.edu               OpDesc(opClass='FloatCmp', opLat=6),
737119Sgblack@eecs.umich.edu               OpDesc(opClass='FloatCvt', opLat=6),
747119Sgblack@eecs.umich.edu               OpDesc(opClass='FloatDiv', opLat=15, pipelined=False),
757119Sgblack@eecs.umich.edu               OpDesc(opClass='FloatSqrt', opLat=33),
767119Sgblack@eecs.umich.edu               OpDesc(opClass='FloatMult', opLat=6) ]
777119Sgblack@eecs.umich.edu
787244Sgblack@eecs.umich.edu# Load/Store Units
797336Sgblack@eecs.umich.educlass ex5_LITTLE_MemFU(MinorDefaultMemFU):
807119Sgblack@eecs.umich.edu    opList = [ OpDesc(opClass='MemRead',opLat=1),
817119Sgblack@eecs.umich.edu               OpDesc(opClass='MemWrite',opLat=1) ]
827119Sgblack@eecs.umich.edu
837119Sgblack@eecs.umich.edu# Misc Unit
847119Sgblack@eecs.umich.educlass ex5_LITTLE_MiscFU(MinorDefaultMiscFU):
857119Sgblack@eecs.umich.edu    opList = [ OpDesc(opClass='IprAccess',opLat=1),
867119Sgblack@eecs.umich.edu               OpDesc(opClass='InstPrefetch',opLat=1) ]
877119Sgblack@eecs.umich.edu
887119Sgblack@eecs.umich.edu# Functional Units for this CPU
897119Sgblack@eecs.umich.educlass ex5_LITTLE_FUP(MinorFUPool):
907119Sgblack@eecs.umich.edu    funcUnits = [ex5_LITTLE_Simple_Int(), ex5_LITTLE_Simple_Int(),
917119Sgblack@eecs.umich.edu        ex5_LITTLE_Complex_IntMul(), ex5_LITTLE_Complex_IntDiv(),
927119Sgblack@eecs.umich.edu        ex5_LITTLE_FP(), ex5_LITTLE_MemFU(),
937119Sgblack@eecs.umich.edu        ex5_LITTLE_MiscFU()]
947119Sgblack@eecs.umich.edu
957294Sgblack@eecs.umich.educlass ex5_LITTLE(MinorCPU):
967192Sgblack@eecs.umich.edu    executeFuncUnits = ex5_LITTLE_FUP()
977192Sgblack@eecs.umich.edu
987294Sgblack@eecs.umich.educlass L1Cache(Cache):
997192Sgblack@eecs.umich.edu    tag_latency = 2
1007192Sgblack@eecs.umich.edu    data_latency = 2
1017192Sgblack@eecs.umich.edu    response_latency = 2
1027192Sgblack@eecs.umich.edu    tgts_per_mshr = 8
1037336Sgblack@eecs.umich.edu    # Consider the L2 a victim cache also for clean lines
1047336Sgblack@eecs.umich.edu    writeback_clean = True
1057336Sgblack@eecs.umich.edu
1067336Sgblack@eecs.umich.educlass L1I(L1Cache):
1077192Sgblack@eecs.umich.edu    mshrs = 2
1087244Sgblack@eecs.umich.edu    size = '32kB'
1097294Sgblack@eecs.umich.edu    assoc = 2
1107244Sgblack@eecs.umich.edu    is_read_only = True
1117296Sgblack@eecs.umich.edu    tgts_per_mshr = 20
1127296Sgblack@eecs.umich.edu
1137294Sgblack@eecs.umich.educlass L1D(L1Cache):
1147336Sgblack@eecs.umich.edu    mshrs = 4
1157294Sgblack@eecs.umich.edu    size = '32kB'
1167294Sgblack@eecs.umich.edu    assoc = 4
1177119Sgblack@eecs.umich.edu    write_buffers = 4
1187119Sgblack@eecs.umich.edu
1197132Sgblack@eecs.umich.edu# TLB Cache
1207119Sgblack@eecs.umich.edu# Use a cache as a L2 TLB
1217192Sgblack@eecs.umich.educlass WalkCache(Cache):
1227119Sgblack@eecs.umich.edu    tag_latency = 2
1237292Sgblack@eecs.umich.edu    data_latency = 2
1247292Sgblack@eecs.umich.edu    response_latency = 2
1257292Sgblack@eecs.umich.edu    mshrs = 6
1267292Sgblack@eecs.umich.edu    tgts_per_mshr = 8
1277292Sgblack@eecs.umich.edu    size = '1kB'
1287292Sgblack@eecs.umich.edu    assoc = 2
1297292Sgblack@eecs.umich.edu    write_buffers = 16
1307292Sgblack@eecs.umich.edu    is_read_only = True
1317292Sgblack@eecs.umich.edu    # Writeback clean lines as well
1327292Sgblack@eecs.umich.edu    writeback_clean = True
1337292Sgblack@eecs.umich.edu
1347292Sgblack@eecs.umich.edu# L2 Cache
1357292Sgblack@eecs.umich.educlass L2(Cache):
1367292Sgblack@eecs.umich.edu    tag_latency = 9
1377292Sgblack@eecs.umich.edu    data_latency = 9
1387292Sgblack@eecs.umich.edu    response_latency = 9
1397296Sgblack@eecs.umich.edu    mshrs = 8
1407296Sgblack@eecs.umich.edu    tgts_per_mshr = 12
1417296Sgblack@eecs.umich.edu    size = '512kB'
1427296Sgblack@eecs.umich.edu    assoc = 8
1437296Sgblack@eecs.umich.edu    write_buffers = 16
1447296Sgblack@eecs.umich.edu    prefetch_on_access = True
1457292Sgblack@eecs.umich.edu    clusivity = 'mostly_excl'
1467292Sgblack@eecs.umich.edu    # Simple stride prefetcher
1477292Sgblack@eecs.umich.edu    prefetcher = StridePrefetcher(degree=1, latency = 1)
1487292Sgblack@eecs.umich.edu    tags = BaseSetAssoc()
1497292Sgblack@eecs.umich.edu    repl_policy = RandomRP()
1507292Sgblack@eecs.umich.edu