Simulation.py revision 3681:129a68314264
1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Lisa Hsu 28 29from os import getcwd 30from os.path import join as joinpath 31import m5 32from m5.objects import * 33m5.AddToPath('../common') 34from Caches import L1Cache 35 36def setCPUClass(options): 37 38 atomic = False 39 if options.timing: 40 TmpClass = TimingSimpleCPU 41 elif options.detailed: 42 if not options.caches: 43 print "O3 CPU must be used with caches" 44 sys.exit(1) 45 TmpClass = DerivO3CPU 46 else: 47 TmpClass = AtomicSimpleCPU 48 atomic = True 49 50 CPUClass = None 51 test_mem_mode = 'atomic' 52 53 if not atomic: 54 if options.checkpoint_restore: 55 CPUClass = TmpClass 56 TmpClass = AtomicSimpleCPU 57 else: 58 test_mem_mode = 'timing' 59 60 return (TmpClass, test_mem_mode, CPUClass) 61 62 63def run(options, root, testsys, cpu_class): 64 if options.maxtick: 65 maxtick = options.maxtick 66 elif options.maxtime: 67 simtime = int(options.maxtime * root.clock.value) 68 print "simulating for: ", simtime 69 maxtick = simtime 70 else: 71 maxtick = m5.MaxTick 72 73 if options.checkpoint_dir: 74 cptdir = options.checkpoint_dir 75 else: 76 cptdir = getcwd() 77 78 np = options.num_cpus 79 max_checkpoints = options.max_checkpoints 80 switch_cpus = None 81 82 if cpu_class: 83 switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 84 for i in xrange(np)] 85 86 for i in xrange(np): 87 switch_cpus[i].system = testsys 88 if not m5.build_env['FULL_SYSTEM']: 89 switch_cpus[i].workload = testsys.cpu[i].workload 90 switch_cpus[i].clock = testsys.cpu[0].clock 91 92 root.switch_cpus = switch_cpus 93 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 94 95 if options.standard_switch: 96 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 97 for i in xrange(np)] 98 switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 99 for i in xrange(np)] 100 101 for i in xrange(np): 102 switch_cpus[i].system = testsys 103 switch_cpus_1[i].system = testsys 104 if not m5.build_env['FULL_SYSTEM']: 105 switch_cpus[i].workload = testsys.cpu[i].workload 106 switch_cpus_1[i].workload = testsys.cpu[i].workload 107 switch_cpus[i].clock = testsys.cpu[0].clock 108 switch_cpus_1[i].clock = testsys.cpu[0].clock 109 110 if not options.caches: 111 # O3 CPU must have a cache to work. 112 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 113 L1Cache(size = '64kB')) 114 switch_cpus_1[i].connectMemPorts(testsys.membus) 115 116 117 testsys.switch_cpus = switch_cpus 118 testsys.switch_cpus_1 = switch_cpus_1 119 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 120 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 121 122 m5.instantiate(root) 123 124 if options.checkpoint_restore: 125 from os.path import isdir 126 from os import listdir 127 import re 128 129 if not isdir(cptdir): 130 m5.panic("checkpoint dir %s does not exist!" % cptdir) 131 132 dirs = listdir(cptdir) 133 expr = re.compile('cpt.([0-9]*)') 134 cpts = [] 135 for dir in dirs: 136 match = expr.match(dir) 137 if match: 138 cpts.append(match.group(1)) 139 140 cpts.sort(lambda a,b: cmp(long(a), long(b))) 141 142 cpt_num = options.checkpoint_restore 143 144 if cpt_num > len(cpts): 145 m5.panic('Checkpoint %d not found' % cpt_num) 146 147 m5.restoreCheckpoint(root, 148 joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1])) 149 150 if options.standard_switch or cpu_class: 151 exit_event = m5.simulate(10000) 152 153 ## when you change to Timing (or Atomic), you halt the system given 154 ## as argument. When you are finished with the system changes 155 ## (including switchCpus), you must resume the system manually. 156 ## You DON'T need to resume after just switching CPUs if you haven't 157 ## changed anything on the system level. 158 159 m5.changeToTiming(testsys) 160 m5.switchCpus(switch_cpu_list) 161 m5.resume(testsys) 162 163 if options.standard_switch: 164 exit_event = m5.simulate(options.warmup) 165 m5.switchCpus(switch_cpu_list1) 166 167 num_checkpoints = 0 168 exit_cause = '' 169 170 ## Checkpoints being taken via the command line at <when> and at subsequent 171 ## periods of <period>. Checkpoint instructions received from the benchmark running 172 ## are ignored and skipped in favor of command line checkpoint instructions. 173 if options.take_checkpoints: 174 [when, period] = options.take_checkpoints.split(",", 1) 175 when = int(when) 176 period = int(period) 177 178 exit_event = m5.simulate(when) 179 while exit_event.getCause() == "checkpoint": 180 exit_event = m5.simulate(when - m5.curTick()) 181 182 if exit_event.getCause() == "simulate() limit reached": 183 m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) 184 num_checkpoints += 1 185 186 sim_ticks = when 187 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 188 while num_checkpoints < max_checkpoints: 189 if (sim_ticks + period) > maxtick: 190 exit_event = m5.simulate(maxtick - sim_ticks) 191 exit_cause = exit_event.getCause() 192 break 193 else: 194 exit_event = m5.simulate(period) 195 sim_ticks += period 196 while exit_event.getCause() == "checkpoint": 197 exit_event = m5.simulate(sim_ticks - m5.curTick()) 198 if exit_event.getCause() == "simulate() limit reached": 199 m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) 200 num_checkpoints += 1 201 202 else: #no checkpoints being taken via this script 203 exit_event = m5.simulate(maxtick) 204 205 while exit_event.getCause() == "checkpoint": 206 m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) 207 num_checkpoints += 1 208 if num_checkpoints == max_checkpoints: 209 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 210 break 211 212 exit_event = m5.simulate(maxtick - m5.curTick()) 213 exit_cause = exit_event.getCause() 214 215 if exit_cause == '': 216 exit_cause = exit_event.getCause() 217 print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) 218 219