Simulation.py revision 9867
19793Sakash.bagdia@arm.com# Copyright (c) 2012-2013 ARM Limited 29518SAndreas.Sandberg@ARM.com# All rights reserved 39518SAndreas.Sandberg@ARM.com# 49518SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59518SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69518SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79518SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89518SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99518SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109518SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119518SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129518SAndreas.Sandberg@ARM.com# 135347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 147534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 153395Shsul@eecs.umich.edu# All rights reserved. 163395Shsul@eecs.umich.edu# 173395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 183395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 193395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 203395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 213395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 223395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 233395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 243395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 253395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 263395Shsul@eecs.umich.edu# this software without specific prior written permission. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393395Shsul@eecs.umich.edu# 403395Shsul@eecs.umich.edu# Authors: Lisa Hsu 413395Shsul@eecs.umich.edu 429457Svilanova@ac.upc.eduimport sys 433395Shsul@eecs.umich.edufrom os import getcwd 443509Shsul@eecs.umich.edufrom os.path import join as joinpath 456654Snate@binkert.org 469520SAndreas.Sandberg@ARM.comimport CpuConfig 479665Sandreas.hansson@arm.comimport MemConfig 489520SAndreas.Sandberg@ARM.com 493395Shsul@eecs.umich.eduimport m5 506654Snate@binkert.orgfrom m5.defines import buildEnv 513395Shsul@eecs.umich.edufrom m5.objects import * 526654Snate@binkert.orgfrom m5.util import * 536654Snate@binkert.org 546654Snate@binkert.orgaddToPath('../common') 553395Shsul@eecs.umich.edu 569139Snilay@cs.wisc.edudef getCPUClass(cpu_type): 579520SAndreas.Sandberg@ARM.com """Returns the required cpu class and the mode of operation.""" 589520SAndreas.Sandberg@ARM.com cls = CpuConfig.get(cpu_type) 599520SAndreas.Sandberg@ARM.com return cls, cls.memory_mode() 609139Snilay@cs.wisc.edu 613481Shsul@eecs.umich.edudef setCPUClass(options): 629139Snilay@cs.wisc.edu """Returns two cpu classes and the initial mode of operation. 633481Shsul@eecs.umich.edu 649139Snilay@cs.wisc.edu Restoring from a checkpoint or fast forwarding through a benchmark 659139Snilay@cs.wisc.edu can be done using one type of cpu, and then the actual 669139Snilay@cs.wisc.edu simulation can be carried out using another type. This function 679139Snilay@cs.wisc.edu returns these two types of cpus and the initial mode of operation 689139Snilay@cs.wisc.edu depending on the options provided. 699139Snilay@cs.wisc.edu """ 709139Snilay@cs.wisc.edu 719139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.cpu_type) 723481Shsul@eecs.umich.edu CPUClass = None 739518SAndreas.Sandberg@ARM.com if TmpClass.require_caches() and \ 749518SAndreas.Sandberg@ARM.com not options.caches and not options.ruby: 759518SAndreas.Sandberg@ARM.com fatal("%s must be used with caches" % options.cpu_type) 763481Shsul@eecs.umich.edu 779139Snilay@cs.wisc.edu if options.checkpoint_restore != None: 789139Snilay@cs.wisc.edu if options.restore_with_cpu != options.cpu_type: 793481Shsul@eecs.umich.edu CPUClass = TmpClass 809139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu) 819139Snilay@cs.wisc.edu elif options.fast_forward: 829139Snilay@cs.wisc.edu CPUClass = TmpClass 839139Snilay@cs.wisc.edu TmpClass = AtomicSimpleCPU 849139Snilay@cs.wisc.edu test_mem_mode = 'atomic' 853481Shsul@eecs.umich.edu 863481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 873481Shsul@eecs.umich.edu 889665Sandreas.hansson@arm.comdef setMemClass(options): 899665Sandreas.hansson@arm.com """Returns a memory controller class.""" 909665Sandreas.hansson@arm.com 919665Sandreas.hansson@arm.com return MemConfig.get(options.mem_type) 929665Sandreas.hansson@arm.com 938919Snilay@cs.wisc.edudef setWorkCountOptions(system, options): 948919Snilay@cs.wisc.edu if options.work_item_id != None: 958919Snilay@cs.wisc.edu system.work_item_id = options.work_item_id 968919Snilay@cs.wisc.edu if options.work_begin_cpu_id_exit != None: 978919Snilay@cs.wisc.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 988919Snilay@cs.wisc.edu if options.work_end_exit_count != None: 998919Snilay@cs.wisc.edu system.work_end_exit_count = options.work_end_exit_count 1008919Snilay@cs.wisc.edu if options.work_end_checkpoint_count != None: 1018919Snilay@cs.wisc.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 1028919Snilay@cs.wisc.edu if options.work_begin_exit_count != None: 1038919Snilay@cs.wisc.edu system.work_begin_exit_count = options.work_begin_exit_count 1048919Snilay@cs.wisc.edu if options.work_begin_checkpoint_count != None: 1058919Snilay@cs.wisc.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 1068919Snilay@cs.wisc.edu if options.work_cpus_checkpoint_count != None: 1078919Snilay@cs.wisc.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 1083481Shsul@eecs.umich.edu 1099816Sjthestness@gmail.comdef findCptDir(options, cptdir, testsys): 1109140Snilay@cs.wisc.edu """Figures out the directory from which the checkpointed state is read. 1119140Snilay@cs.wisc.edu 1129140Snilay@cs.wisc.edu There are two different ways in which the directories holding checkpoints 1139140Snilay@cs.wisc.edu can be named -- 1149140Snilay@cs.wisc.edu 1. cpt.<benchmark name>.<instruction count when the checkpoint was taken> 1159140Snilay@cs.wisc.edu 2. cpt.<some number, usually the tick value when the checkpoint was taken> 1169140Snilay@cs.wisc.edu 1179140Snilay@cs.wisc.edu This function parses through the options to figure out which one of the 1189140Snilay@cs.wisc.edu above should be used for selecting the checkpoint, and then figures out 1199140Snilay@cs.wisc.edu the appropriate directory. 1209140Snilay@cs.wisc.edu """ 1219140Snilay@cs.wisc.edu 1229140Snilay@cs.wisc.edu from os.path import isdir, exists 1239140Snilay@cs.wisc.edu from os import listdir 1249140Snilay@cs.wisc.edu import re 1259140Snilay@cs.wisc.edu 1269140Snilay@cs.wisc.edu if not isdir(cptdir): 1279140Snilay@cs.wisc.edu fatal("checkpoint dir %s does not exist!", cptdir) 1289140Snilay@cs.wisc.edu 1299867Sjthestness@gmail.com cpt_starttick = 0 1309140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1319140Snilay@cs.wisc.edu inst = options.checkpoint_restore 1329140Snilay@cs.wisc.edu if options.simpoint: 1339140Snilay@cs.wisc.edu # assume workload 0 has the simpoint 1349140Snilay@cs.wisc.edu if testsys.cpu[0].workload[0].simpoint == 0: 1359140Snilay@cs.wisc.edu fatal('Unable to find simpoint') 1369140Snilay@cs.wisc.edu inst += int(testsys.cpu[0].workload[0].simpoint) 1379140Snilay@cs.wisc.edu 1389140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) 1399140Snilay@cs.wisc.edu if not exists(checkpoint_dir): 1409140Snilay@cs.wisc.edu fatal("Unable to find checkpoint directory %s", checkpoint_dir) 1419140Snilay@cs.wisc.edu else: 1429140Snilay@cs.wisc.edu dirs = listdir(cptdir) 1439140Snilay@cs.wisc.edu expr = re.compile('cpt\.([0-9]*)') 1449140Snilay@cs.wisc.edu cpts = [] 1459140Snilay@cs.wisc.edu for dir in dirs: 1469140Snilay@cs.wisc.edu match = expr.match(dir) 1479140Snilay@cs.wisc.edu if match: 1489140Snilay@cs.wisc.edu cpts.append(match.group(1)) 1499140Snilay@cs.wisc.edu 1509140Snilay@cs.wisc.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 1519140Snilay@cs.wisc.edu 1529140Snilay@cs.wisc.edu cpt_num = options.checkpoint_restore 1539140Snilay@cs.wisc.edu if cpt_num > len(cpts): 1549140Snilay@cs.wisc.edu fatal('Checkpoint %d not found', cpt_num) 1559140Snilay@cs.wisc.edu 1569816Sjthestness@gmail.com cpt_starttick = int(cpts[cpt_num - 1]) 1579140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 1589140Snilay@cs.wisc.edu 1599816Sjthestness@gmail.com return cpt_starttick, checkpoint_dir 1609140Snilay@cs.wisc.edu 1619215Sandreas.hansson@arm.comdef scriptCheckpoints(options, maxtick, cptdir): 1629140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1639140Snilay@cs.wisc.edu checkpoint_inst = int(options.take_checkpoints) 1649140Snilay@cs.wisc.edu 1659140Snilay@cs.wisc.edu # maintain correct offset if we restored from some instruction 1669140Snilay@cs.wisc.edu if options.checkpoint_restore != None: 1679140Snilay@cs.wisc.edu checkpoint_inst += options.checkpoint_restore 1689140Snilay@cs.wisc.edu 1699140Snilay@cs.wisc.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 1709140Snilay@cs.wisc.edu exit_event = m5.simulate() 1719140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1729140Snilay@cs.wisc.edu print "exit cause = %s" % exit_cause 1739140Snilay@cs.wisc.edu 1749140Snilay@cs.wisc.edu # skip checkpoint instructions should they exist 1759140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 1769140Snilay@cs.wisc.edu exit_event = m5.simulate() 1779140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1789140Snilay@cs.wisc.edu 1799140Snilay@cs.wisc.edu if exit_cause == "a thread reached the max instruction count": 1809140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 1819140Snilay@cs.wisc.edu (options.bench, checkpoint_inst))) 1829140Snilay@cs.wisc.edu print "Checkpoint written." 1839140Snilay@cs.wisc.edu 1849140Snilay@cs.wisc.edu else: 1859140Snilay@cs.wisc.edu when, period = options.take_checkpoints.split(",", 1) 1869140Snilay@cs.wisc.edu when = int(when) 1879140Snilay@cs.wisc.edu period = int(period) 1889156Sandreas.hansson@arm.com num_checkpoints = 0 1899140Snilay@cs.wisc.edu 1909634Sjthestness@gmail.com exit_event = m5.simulate(when - m5.curTick()) 1919140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1929140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 1939140Snilay@cs.wisc.edu exit_event = m5.simulate(when - m5.curTick()) 1949140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1959140Snilay@cs.wisc.edu 1969140Snilay@cs.wisc.edu if exit_cause == "simulate() limit reached": 1979140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 1989140Snilay@cs.wisc.edu num_checkpoints += 1 1999140Snilay@cs.wisc.edu 2009140Snilay@cs.wisc.edu sim_ticks = when 2019140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2029140Snilay@cs.wisc.edu 2039140Snilay@cs.wisc.edu while num_checkpoints < max_checkpoints and \ 2049140Snilay@cs.wisc.edu exit_cause == "simulate() limit reached": 2059140Snilay@cs.wisc.edu if (sim_ticks + period) > maxtick: 2069140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - sim_ticks) 2079140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2089140Snilay@cs.wisc.edu break 2099140Snilay@cs.wisc.edu else: 2109140Snilay@cs.wisc.edu exit_event = m5.simulate(period) 2119140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2129140Snilay@cs.wisc.edu sim_ticks += period 2139140Snilay@cs.wisc.edu while exit_event.getCause() == "checkpoint": 2149140Snilay@cs.wisc.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 2159140Snilay@cs.wisc.edu if exit_event.getCause() == "simulate() limit reached": 2169140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2179140Snilay@cs.wisc.edu num_checkpoints += 1 2189140Snilay@cs.wisc.edu 2199606Snilay@cs.wisc.edu return exit_event 2209140Snilay@cs.wisc.edu 2219140Snilay@cs.wisc.edudef benchCheckpoints(options, maxtick, cptdir): 2229634Sjthestness@gmail.com exit_event = m5.simulate(maxtick - m5.curTick()) 2239140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2249140Snilay@cs.wisc.edu 2259140Snilay@cs.wisc.edu num_checkpoints = 0 2269140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2279140Snilay@cs.wisc.edu 2289140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2299140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2309140Snilay@cs.wisc.edu num_checkpoints += 1 2319140Snilay@cs.wisc.edu if num_checkpoints == max_checkpoints: 2329140Snilay@cs.wisc.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 2339140Snilay@cs.wisc.edu break 2349140Snilay@cs.wisc.edu 2359140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2369140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2379140Snilay@cs.wisc.edu 2389460Ssaidi@eecs.umich.edu return exit_event 2399140Snilay@cs.wisc.edu 2409151Satgutier@umich.edudef repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, switch_freq): 2419151Satgutier@umich.edu print "starting switch loop" 2429151Satgutier@umich.edu while True: 2439151Satgutier@umich.edu exit_event = m5.simulate(switch_freq) 2449151Satgutier@umich.edu exit_cause = exit_event.getCause() 2459151Satgutier@umich.edu 2469151Satgutier@umich.edu if exit_cause != "simulate() limit reached": 2479460Ssaidi@eecs.umich.edu return exit_event 2489151Satgutier@umich.edu 2499521SAndreas.Sandberg@ARM.com m5.switchCpus(testsys, repeat_switch_cpu_list) 2509151Satgutier@umich.edu 2519151Satgutier@umich.edu tmp_cpu_list = [] 2529151Satgutier@umich.edu for old_cpu, new_cpu in repeat_switch_cpu_list: 2539151Satgutier@umich.edu tmp_cpu_list.append((new_cpu, old_cpu)) 2549151Satgutier@umich.edu repeat_switch_cpu_list = tmp_cpu_list 2559151Satgutier@umich.edu 2569151Satgutier@umich.edu if (maxtick - m5.curTick()) <= switch_freq: 2579151Satgutier@umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2589460Ssaidi@eecs.umich.edu return exit_event 2599151Satgutier@umich.edu 2603481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 2613395Shsul@eecs.umich.edu if options.checkpoint_dir: 2623395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 2635211Ssaidi@eecs.umich.edu elif m5.options.outdir: 2645211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 2653395Shsul@eecs.umich.edu else: 2663395Shsul@eecs.umich.edu cptdir = getcwd() 2673395Shsul@eecs.umich.edu 2685370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 2696654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 2705370Ssaidi@eecs.umich.edu 2715371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 2726654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 2735370Ssaidi@eecs.umich.edu 2749151Satgutier@umich.edu if options.standard_switch and options.repeat_switch: 2759151Satgutier@umich.edu fatal("Can't specify both --standard-switch and --repeat-switch") 2769151Satgutier@umich.edu 2779151Satgutier@umich.edu if options.repeat_switch and options.take_checkpoints: 2789151Satgutier@umich.edu fatal("Can't specify both --repeat-switch and --take-checkpoints") 2799151Satgutier@umich.edu 2803395Shsul@eecs.umich.edu np = options.num_cpus 2813481Shsul@eecs.umich.edu switch_cpus = None 2823481Shsul@eecs.umich.edu 2838318Sksewell@umich.edu if options.prog_interval: 2846144Sksewell@umich.edu for i in xrange(np): 2858311Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_interval 2866144Sksewell@umich.edu 2876641Sksewell@umich.edu if options.maxinsts: 2886641Sksewell@umich.edu for i in xrange(np): 2896641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 2906641Sksewell@umich.edu 2913481Shsul@eecs.umich.edu if cpu_class: 2929433SAndreas.Sandberg@ARM.com switch_cpus = [cpu_class(switched_out=True, cpu_id=(i)) 2933481Shsul@eecs.umich.edu for i in xrange(np)] 2943481Shsul@eecs.umich.edu 2953481Shsul@eecs.umich.edu for i in xrange(np): 2965361Srstrong@cs.ucsd.edu if options.fast_forward: 2975369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 2983481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 2998803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 3009793Sakash.bagdia@arm.com switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain 3015369Ssaidi@eecs.umich.edu # simulation period 3028311Sksewell@umich.edu if options.maxinsts: 3038311Sksewell@umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 3048887Sgeoffrey.blake@arm.com # Add checker cpu if selected 3058887Sgeoffrey.blake@arm.com if options.checker: 3068887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 3073481Shsul@eecs.umich.edu 3085311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 3093481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 3103395Shsul@eecs.umich.edu 3119151Satgutier@umich.edu if options.repeat_switch: 3129518SAndreas.Sandberg@ARM.com switch_class = getCPUClass(options.cpu_type)[0] 3139518SAndreas.Sandberg@ARM.com if switch_class.require_caches() and \ 3149518SAndreas.Sandberg@ARM.com not options.caches: 3159518SAndreas.Sandberg@ARM.com print "%s: Must be used with caches" % str(switch_class) 3169518SAndreas.Sandberg@ARM.com sys.exit(1) 3179518SAndreas.Sandberg@ARM.com if not switch_class.support_take_over(): 3189518SAndreas.Sandberg@ARM.com print "%s: CPU switching not supported" % str(switch_class) 3199518SAndreas.Sandberg@ARM.com sys.exit(1) 3209151Satgutier@umich.edu 3219518SAndreas.Sandberg@ARM.com repeat_switch_cpus = [switch_class(switched_out=True, \ 3229518SAndreas.Sandberg@ARM.com cpu_id=(i)) for i in xrange(np)] 3239151Satgutier@umich.edu 3249151Satgutier@umich.edu for i in xrange(np): 3259151Satgutier@umich.edu repeat_switch_cpus[i].system = testsys 3269151Satgutier@umich.edu repeat_switch_cpus[i].workload = testsys.cpu[i].workload 3279793Sakash.bagdia@arm.com repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain 3289151Satgutier@umich.edu 3299151Satgutier@umich.edu if options.maxinsts: 3309151Satgutier@umich.edu repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts 3319151Satgutier@umich.edu 3329151Satgutier@umich.edu if options.checker: 3339151Satgutier@umich.edu repeat_switch_cpus[i].addCheckerCpu() 3349151Satgutier@umich.edu 3359151Satgutier@umich.edu testsys.repeat_switch_cpus = repeat_switch_cpus 3369151Satgutier@umich.edu 3379151Satgutier@umich.edu if cpu_class: 3389151Satgutier@umich.edu repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) 3399151Satgutier@umich.edu for i in xrange(np)] 3409151Satgutier@umich.edu else: 3419151Satgutier@umich.edu repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) 3429151Satgutier@umich.edu for i in xrange(np)] 3439151Satgutier@umich.edu 3443395Shsul@eecs.umich.edu if options.standard_switch: 3459433SAndreas.Sandberg@ARM.com switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i)) 3463395Shsul@eecs.umich.edu for i in xrange(np)] 3479433SAndreas.Sandberg@ARM.com switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i)) 3483395Shsul@eecs.umich.edu for i in xrange(np)] 3493478Shsul@eecs.umich.edu 3503395Shsul@eecs.umich.edu for i in xrange(np): 3513395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 3523478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 3538803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 3548803Sgblack@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 3559793Sakash.bagdia@arm.com switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain 3569793Sakash.bagdia@arm.com switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain 3573480Shsul@eecs.umich.edu 3585361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 3595369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 3605361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 3615361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 3625361Srstrong@cs.ucsd.edu elif options.fast_forward: 3635369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 3645361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 3655361Srstrong@cs.ucsd.edu elif options.simpoint: 3665378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 3676654Snate@binkert.org fatal('simpoint not found') 3685361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 3695361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 3705361Srstrong@cs.ucsd.edu # No distance specified, just switch 3715361Srstrong@cs.ucsd.edu else: 3725361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 3735361Srstrong@cs.ucsd.edu 3745361Srstrong@cs.ucsd.edu # warmup period 3755361Srstrong@cs.ucsd.edu if options.warmup_insts: 3765361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 3775361Srstrong@cs.ucsd.edu 3785361Srstrong@cs.ucsd.edu # simulation period 3798311Sksewell@umich.edu if options.maxinsts: 3808311Sksewell@umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 3815353Svilas.sridharan@gmail.com 3828887Sgeoffrey.blake@arm.com # attach the checker cpu if selected 3838887Sgeoffrey.blake@arm.com if options.checker: 3848887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 3858887Sgeoffrey.blake@arm.com switch_cpus_1[i].addCheckerCpu() 3868887Sgeoffrey.blake@arm.com 3878211Satgutier@umich.edu testsys.switch_cpus = switch_cpus 3888211Satgutier@umich.edu testsys.switch_cpus_1 = switch_cpus_1 3898211Satgutier@umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 3908211Satgutier@umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 3913395Shsul@eecs.umich.edu 3925361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 3935369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 3945361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 3955361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 3965361Srstrong@cs.ucsd.edu # Set an instruction break point 3975361Srstrong@cs.ucsd.edu if options.simpoint: 3985361Srstrong@cs.ucsd.edu for i in xrange(np): 3995378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 4006654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 4015369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 4025361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 4035361Srstrong@cs.ucsd.edu # used for output below 4045361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 4055361Srstrong@cs.ucsd.edu else: 4065361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 4075361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 4085361Srstrong@cs.ucsd.edu # for the upcoming simulation 4095361Srstrong@cs.ucsd.edu for i in xrange(np): 4105361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 4115361Srstrong@cs.ucsd.edu 4127531Ssteve.reinhardt@amd.com checkpoint_dir = None 4139816Sjthestness@gmail.com if options.checkpoint_restore: 4149816Sjthestness@gmail.com cpt_starttick, checkpoint_dir = findCptDir(options, cptdir, testsys) 4157531Ssteve.reinhardt@amd.com m5.instantiate(checkpoint_dir) 4163395Shsul@eecs.umich.edu 4179816Sjthestness@gmail.com # Handle the max tick settings now that tick frequency was resolved 4189816Sjthestness@gmail.com # during system instantiation 4199816Sjthestness@gmail.com # NOTE: the maxtick variable here is in absolute ticks, so it must 4209816Sjthestness@gmail.com # include any simulated ticks before a checkpoint 4219816Sjthestness@gmail.com explicit_maxticks = 0 4229816Sjthestness@gmail.com maxtick_from_abs = m5.MaxTick 4239816Sjthestness@gmail.com maxtick_from_rel = m5.MaxTick 4249816Sjthestness@gmail.com maxtick_from_maxtime = m5.MaxTick 4259816Sjthestness@gmail.com if options.abs_max_tick: 4269816Sjthestness@gmail.com maxtick_from_abs = options.abs_max_tick 4279816Sjthestness@gmail.com explicit_maxticks += 1 4289816Sjthestness@gmail.com if options.rel_max_tick: 4299816Sjthestness@gmail.com maxtick_from_rel = options.rel_max_tick 4309816Sjthestness@gmail.com if options.checkpoint_restore: 4319816Sjthestness@gmail.com # NOTE: this may need to be updated if checkpoints ever store 4329816Sjthestness@gmail.com # the ticks per simulated second 4339816Sjthestness@gmail.com maxtick_from_rel += cpt_starttick 4349867Sjthestness@gmail.com if options.at_instruction or options.simpoint: 4359867Sjthestness@gmail.com warn("Relative max tick specified with --at-instruction or" \ 4369867Sjthestness@gmail.com " --simpoint\n These options don't specify the " \ 4379867Sjthestness@gmail.com "checkpoint start tick, so assuming\n you mean " \ 4389867Sjthestness@gmail.com "absolute max tick") 4399816Sjthestness@gmail.com explicit_maxticks += 1 4409816Sjthestness@gmail.com if options.maxtime: 4419816Sjthestness@gmail.com maxtick_from_maxtime = m5.ticks.fromSeconds(options.maxtime) 4429816Sjthestness@gmail.com explicit_maxticks += 1 4439816Sjthestness@gmail.com if explicit_maxticks > 1: 4449816Sjthestness@gmail.com warn("Specified multiple of --abs-max-tick, --rel-max-tick, --maxtime."\ 4459816Sjthestness@gmail.com " Using least") 4469816Sjthestness@gmail.com maxtick = min([maxtick_from_abs, maxtick_from_rel, maxtick_from_maxtime]) 4479816Sjthestness@gmail.com 4489816Sjthestness@gmail.com if options.checkpoint_restore != None and maxtick < cpt_starttick: 4499816Sjthestness@gmail.com fatal("Bad maxtick (%d) specified: " \ 4509816Sjthestness@gmail.com "Checkpoint starts starts from tick: %d", maxtick, cpt_starttick) 4519816Sjthestness@gmail.com 4523481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 4535361Srstrong@cs.ucsd.edu if options.standard_switch: 4545361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 4555361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 4565361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4575361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 4585361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 4595361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 4605361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4615361Srstrong@cs.ucsd.edu else: 4625361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 4635361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 4647766Sgblack@eecs.umich.edu print "Switched CPUS @ tick %s" % (m5.curTick()) 4653395Shsul@eecs.umich.edu 4669521SAndreas.Sandberg@ARM.com m5.switchCpus(testsys, switch_cpu_list) 4673395Shsul@eecs.umich.edu 4683481Shsul@eecs.umich.edu if options.standard_switch: 4695361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 4705361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 4715361Srstrong@cs.ucsd.edu 4725361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 4735361Srstrong@cs.ucsd.edu if options.warmup_insts: 4745361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4755361Srstrong@cs.ucsd.edu else: 4769151Satgutier@umich.edu exit_event = m5.simulate(options.standard_switch) 4777766Sgblack@eecs.umich.edu print "Switching CPUS @ tick %s" % (m5.curTick()) 4785361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 4795361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 4809521SAndreas.Sandberg@ARM.com m5.switchCpus(testsys, switch_cpu_list1) 4813395Shsul@eecs.umich.edu 4827489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 4837489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 4847489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 4857489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 4867489Ssteve.reinhardt@amd.com if options.take_checkpoints and options.checkpoint_restore: 4877489Ssteve.reinhardt@amd.com if m5.options.outdir: 4887489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 4897489Ssteve.reinhardt@amd.com else: 4907489Ssteve.reinhardt@amd.com cptdir = getcwd() 4917489Ssteve.reinhardt@amd.com 4925369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 4939140Snilay@cs.wisc.edu # Checkpoints being taken via the command line at <when> and at 4949140Snilay@cs.wisc.edu # subsequent periods of <period>. Checkpoint instructions 4959140Snilay@cs.wisc.edu # received from the benchmark running are ignored and skipped in 4969140Snilay@cs.wisc.edu # favor of command line checkpoint instructions. 4979606Snilay@cs.wisc.edu exit_event = scriptCheckpoints(options, maxtick, cptdir) 4989140Snilay@cs.wisc.edu else: 4999151Satgutier@umich.edu if options.fast_forward: 5009151Satgutier@umich.edu m5.stats.reset() 5019151Satgutier@umich.edu print "**** REAL SIMULATION ****" 5029151Satgutier@umich.edu 5039140Snilay@cs.wisc.edu # If checkpoints are being taken, then the checkpoint instruction 5049140Snilay@cs.wisc.edu # will occur in the benchmark code it self. 5059151Satgutier@umich.edu if options.repeat_switch and maxtick > options.repeat_switch: 5069460Ssaidi@eecs.umich.edu exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, 5079151Satgutier@umich.edu maxtick, options.repeat_switch) 5089151Satgutier@umich.edu else: 5099460Ssaidi@eecs.umich.edu exit_event = benchCheckpoints(options, maxtick, cptdir) 5103395Shsul@eecs.umich.edu 5119460Ssaidi@eecs.umich.edu print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) 5126776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 5137525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 5149457Svilanova@ac.upc.edu 5159494Sandreas@sandberg.pp.se if not m5.options.interactive: 5169494Sandreas@sandberg.pp.se sys.exit(exit_event.getCode()) 517