Simulation.py revision 9518
19518SAndreas.Sandberg@ARM.com# Copyright (c) 2012 ARM Limited 29518SAndreas.Sandberg@ARM.com# All rights reserved 39518SAndreas.Sandberg@ARM.com# 49518SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59518SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69518SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79518SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89518SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99518SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109518SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119518SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129518SAndreas.Sandberg@ARM.com# 135347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 147534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 153395Shsul@eecs.umich.edu# All rights reserved. 163395Shsul@eecs.umich.edu# 173395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 183395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 193395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 203395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 213395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 223395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 233395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 243395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 253395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 263395Shsul@eecs.umich.edu# this software without specific prior written permission. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393395Shsul@eecs.umich.edu# 403395Shsul@eecs.umich.edu# Authors: Lisa Hsu 413395Shsul@eecs.umich.edu 429457Svilanova@ac.upc.eduimport sys 433395Shsul@eecs.umich.edufrom os import getcwd 443509Shsul@eecs.umich.edufrom os.path import join as joinpath 456654Snate@binkert.org 463395Shsul@eecs.umich.eduimport m5 476654Snate@binkert.orgfrom m5.defines import buildEnv 483395Shsul@eecs.umich.edufrom m5.objects import * 496654Snate@binkert.orgfrom m5.util import * 508724Srdreslin@umich.edufrom O3_ARM_v7a import * 516654Snate@binkert.org 526654Snate@binkert.orgaddToPath('../common') 533395Shsul@eecs.umich.edu 549139Snilay@cs.wisc.edudef getCPUClass(cpu_type): 559139Snilay@cs.wisc.edu """Returns the required cpu class and the mode of operation. 569139Snilay@cs.wisc.edu """ 579139Snilay@cs.wisc.edu 589139Snilay@cs.wisc.edu if cpu_type == "timing": 599139Snilay@cs.wisc.edu return TimingSimpleCPU, 'timing' 609139Snilay@cs.wisc.edu elif cpu_type == "detailed": 619139Snilay@cs.wisc.edu return DerivO3CPU, 'timing' 629139Snilay@cs.wisc.edu elif cpu_type == "arm_detailed": 639139Snilay@cs.wisc.edu return O3_ARM_v7a_3, 'timing' 649139Snilay@cs.wisc.edu elif cpu_type == "inorder": 659139Snilay@cs.wisc.edu return InOrderCPU, 'timing' 669139Snilay@cs.wisc.edu else: 679139Snilay@cs.wisc.edu return AtomicSimpleCPU, 'atomic' 689139Snilay@cs.wisc.edu 693481Shsul@eecs.umich.edudef setCPUClass(options): 709139Snilay@cs.wisc.edu """Returns two cpu classes and the initial mode of operation. 713481Shsul@eecs.umich.edu 729139Snilay@cs.wisc.edu Restoring from a checkpoint or fast forwarding through a benchmark 739139Snilay@cs.wisc.edu can be done using one type of cpu, and then the actual 749139Snilay@cs.wisc.edu simulation can be carried out using another type. This function 759139Snilay@cs.wisc.edu returns these two types of cpus and the initial mode of operation 769139Snilay@cs.wisc.edu depending on the options provided. 779139Snilay@cs.wisc.edu """ 789139Snilay@cs.wisc.edu 799139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.cpu_type) 803481Shsul@eecs.umich.edu CPUClass = None 819518SAndreas.Sandberg@ARM.com if TmpClass.require_caches() and \ 829518SAndreas.Sandberg@ARM.com not options.caches and not options.ruby: 839518SAndreas.Sandberg@ARM.com fatal("%s must be used with caches" % options.cpu_type) 843481Shsul@eecs.umich.edu 859139Snilay@cs.wisc.edu if options.checkpoint_restore != None: 869139Snilay@cs.wisc.edu if options.restore_with_cpu != options.cpu_type: 873481Shsul@eecs.umich.edu CPUClass = TmpClass 889139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu) 899139Snilay@cs.wisc.edu elif options.fast_forward: 909139Snilay@cs.wisc.edu CPUClass = TmpClass 919139Snilay@cs.wisc.edu TmpClass = AtomicSimpleCPU 929139Snilay@cs.wisc.edu test_mem_mode = 'atomic' 933481Shsul@eecs.umich.edu 943481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 953481Shsul@eecs.umich.edu 968919Snilay@cs.wisc.edudef setWorkCountOptions(system, options): 978919Snilay@cs.wisc.edu if options.work_item_id != None: 988919Snilay@cs.wisc.edu system.work_item_id = options.work_item_id 998919Snilay@cs.wisc.edu if options.work_begin_cpu_id_exit != None: 1008919Snilay@cs.wisc.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 1018919Snilay@cs.wisc.edu if options.work_end_exit_count != None: 1028919Snilay@cs.wisc.edu system.work_end_exit_count = options.work_end_exit_count 1038919Snilay@cs.wisc.edu if options.work_end_checkpoint_count != None: 1048919Snilay@cs.wisc.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 1058919Snilay@cs.wisc.edu if options.work_begin_exit_count != None: 1068919Snilay@cs.wisc.edu system.work_begin_exit_count = options.work_begin_exit_count 1078919Snilay@cs.wisc.edu if options.work_begin_checkpoint_count != None: 1088919Snilay@cs.wisc.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 1098919Snilay@cs.wisc.edu if options.work_cpus_checkpoint_count != None: 1108919Snilay@cs.wisc.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 1113481Shsul@eecs.umich.edu 1129140Snilay@cs.wisc.edudef findCptDir(options, maxtick, cptdir, testsys): 1139140Snilay@cs.wisc.edu """Figures out the directory from which the checkpointed state is read. 1149140Snilay@cs.wisc.edu 1159140Snilay@cs.wisc.edu There are two different ways in which the directories holding checkpoints 1169140Snilay@cs.wisc.edu can be named -- 1179140Snilay@cs.wisc.edu 1. cpt.<benchmark name>.<instruction count when the checkpoint was taken> 1189140Snilay@cs.wisc.edu 2. cpt.<some number, usually the tick value when the checkpoint was taken> 1199140Snilay@cs.wisc.edu 1209140Snilay@cs.wisc.edu This function parses through the options to figure out which one of the 1219140Snilay@cs.wisc.edu above should be used for selecting the checkpoint, and then figures out 1229140Snilay@cs.wisc.edu the appropriate directory. 1239140Snilay@cs.wisc.edu 1249140Snilay@cs.wisc.edu It also sets the value of the maximum tick value till which the simulation 1259140Snilay@cs.wisc.edu will run. 1269140Snilay@cs.wisc.edu """ 1279140Snilay@cs.wisc.edu 1289140Snilay@cs.wisc.edu from os.path import isdir, exists 1299140Snilay@cs.wisc.edu from os import listdir 1309140Snilay@cs.wisc.edu import re 1319140Snilay@cs.wisc.edu 1329140Snilay@cs.wisc.edu if not isdir(cptdir): 1339140Snilay@cs.wisc.edu fatal("checkpoint dir %s does not exist!", cptdir) 1349140Snilay@cs.wisc.edu 1359140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1369140Snilay@cs.wisc.edu inst = options.checkpoint_restore 1379140Snilay@cs.wisc.edu if options.simpoint: 1389140Snilay@cs.wisc.edu # assume workload 0 has the simpoint 1399140Snilay@cs.wisc.edu if testsys.cpu[0].workload[0].simpoint == 0: 1409140Snilay@cs.wisc.edu fatal('Unable to find simpoint') 1419140Snilay@cs.wisc.edu inst += int(testsys.cpu[0].workload[0].simpoint) 1429140Snilay@cs.wisc.edu 1439140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) 1449140Snilay@cs.wisc.edu if not exists(checkpoint_dir): 1459140Snilay@cs.wisc.edu fatal("Unable to find checkpoint directory %s", checkpoint_dir) 1469140Snilay@cs.wisc.edu else: 1479140Snilay@cs.wisc.edu dirs = listdir(cptdir) 1489140Snilay@cs.wisc.edu expr = re.compile('cpt\.([0-9]*)') 1499140Snilay@cs.wisc.edu cpts = [] 1509140Snilay@cs.wisc.edu for dir in dirs: 1519140Snilay@cs.wisc.edu match = expr.match(dir) 1529140Snilay@cs.wisc.edu if match: 1539140Snilay@cs.wisc.edu cpts.append(match.group(1)) 1549140Snilay@cs.wisc.edu 1559140Snilay@cs.wisc.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 1569140Snilay@cs.wisc.edu 1579140Snilay@cs.wisc.edu cpt_num = options.checkpoint_restore 1589140Snilay@cs.wisc.edu if cpt_num > len(cpts): 1599140Snilay@cs.wisc.edu fatal('Checkpoint %d not found', cpt_num) 1609140Snilay@cs.wisc.edu 1619140Snilay@cs.wisc.edu maxtick = maxtick - int(cpts[cpt_num - 1]) 1629140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 1639140Snilay@cs.wisc.edu 1649140Snilay@cs.wisc.edu return maxtick, checkpoint_dir 1659140Snilay@cs.wisc.edu 1669215Sandreas.hansson@arm.comdef scriptCheckpoints(options, maxtick, cptdir): 1679140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1689140Snilay@cs.wisc.edu checkpoint_inst = int(options.take_checkpoints) 1699140Snilay@cs.wisc.edu 1709140Snilay@cs.wisc.edu # maintain correct offset if we restored from some instruction 1719140Snilay@cs.wisc.edu if options.checkpoint_restore != None: 1729140Snilay@cs.wisc.edu checkpoint_inst += options.checkpoint_restore 1739140Snilay@cs.wisc.edu 1749140Snilay@cs.wisc.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 1759140Snilay@cs.wisc.edu exit_event = m5.simulate() 1769140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1779140Snilay@cs.wisc.edu print "exit cause = %s" % exit_cause 1789140Snilay@cs.wisc.edu 1799140Snilay@cs.wisc.edu # skip checkpoint instructions should they exist 1809140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 1819140Snilay@cs.wisc.edu exit_event = m5.simulate() 1829140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1839140Snilay@cs.wisc.edu 1849140Snilay@cs.wisc.edu if exit_cause == "a thread reached the max instruction count": 1859140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 1869140Snilay@cs.wisc.edu (options.bench, checkpoint_inst))) 1879140Snilay@cs.wisc.edu print "Checkpoint written." 1889140Snilay@cs.wisc.edu 1899140Snilay@cs.wisc.edu else: 1909140Snilay@cs.wisc.edu when, period = options.take_checkpoints.split(",", 1) 1919140Snilay@cs.wisc.edu when = int(when) 1929140Snilay@cs.wisc.edu period = int(period) 1939156Sandreas.hansson@arm.com num_checkpoints = 0 1949140Snilay@cs.wisc.edu 1959140Snilay@cs.wisc.edu exit_event = m5.simulate(when) 1969140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1979140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 1989140Snilay@cs.wisc.edu exit_event = m5.simulate(when - m5.curTick()) 1999140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2009140Snilay@cs.wisc.edu 2019140Snilay@cs.wisc.edu if exit_cause == "simulate() limit reached": 2029140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2039140Snilay@cs.wisc.edu num_checkpoints += 1 2049140Snilay@cs.wisc.edu 2059140Snilay@cs.wisc.edu sim_ticks = when 2069140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2079140Snilay@cs.wisc.edu 2089140Snilay@cs.wisc.edu while num_checkpoints < max_checkpoints and \ 2099140Snilay@cs.wisc.edu exit_cause == "simulate() limit reached": 2109140Snilay@cs.wisc.edu if (sim_ticks + period) > maxtick: 2119140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - sim_ticks) 2129140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2139140Snilay@cs.wisc.edu break 2149140Snilay@cs.wisc.edu else: 2159140Snilay@cs.wisc.edu exit_event = m5.simulate(period) 2169140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2179140Snilay@cs.wisc.edu sim_ticks += period 2189140Snilay@cs.wisc.edu while exit_event.getCause() == "checkpoint": 2199140Snilay@cs.wisc.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 2209140Snilay@cs.wisc.edu if exit_event.getCause() == "simulate() limit reached": 2219140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2229140Snilay@cs.wisc.edu num_checkpoints += 1 2239140Snilay@cs.wisc.edu 2249140Snilay@cs.wisc.edu return exit_cause 2259140Snilay@cs.wisc.edu 2269140Snilay@cs.wisc.edudef benchCheckpoints(options, maxtick, cptdir): 2279140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick) 2289140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2299140Snilay@cs.wisc.edu 2309140Snilay@cs.wisc.edu num_checkpoints = 0 2319140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2329140Snilay@cs.wisc.edu 2339140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2349140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2359140Snilay@cs.wisc.edu num_checkpoints += 1 2369140Snilay@cs.wisc.edu if num_checkpoints == max_checkpoints: 2379140Snilay@cs.wisc.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 2389140Snilay@cs.wisc.edu break 2399140Snilay@cs.wisc.edu 2409140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2419140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2429140Snilay@cs.wisc.edu 2439460Ssaidi@eecs.umich.edu return exit_event 2449140Snilay@cs.wisc.edu 2459151Satgutier@umich.edudef repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, switch_freq): 2469151Satgutier@umich.edu print "starting switch loop" 2479151Satgutier@umich.edu while True: 2489151Satgutier@umich.edu exit_event = m5.simulate(switch_freq) 2499151Satgutier@umich.edu exit_cause = exit_event.getCause() 2509151Satgutier@umich.edu 2519151Satgutier@umich.edu if exit_cause != "simulate() limit reached": 2529460Ssaidi@eecs.umich.edu return exit_event 2539151Satgutier@umich.edu 2549151Satgutier@umich.edu print "draining the system" 2559344SAndreas.Sandberg@arm.com m5.drain(testsys) 2569151Satgutier@umich.edu m5.switchCpus(repeat_switch_cpu_list) 2579151Satgutier@umich.edu m5.resume(testsys) 2589151Satgutier@umich.edu 2599151Satgutier@umich.edu tmp_cpu_list = [] 2609151Satgutier@umich.edu for old_cpu, new_cpu in repeat_switch_cpu_list: 2619151Satgutier@umich.edu tmp_cpu_list.append((new_cpu, old_cpu)) 2629151Satgutier@umich.edu repeat_switch_cpu_list = tmp_cpu_list 2639151Satgutier@umich.edu 2649151Satgutier@umich.edu if (maxtick - m5.curTick()) <= switch_freq: 2659151Satgutier@umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2669460Ssaidi@eecs.umich.edu return exit_event 2679151Satgutier@umich.edu 2683481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 2693395Shsul@eecs.umich.edu if options.maxtick: 2703395Shsul@eecs.umich.edu maxtick = options.maxtick 2713395Shsul@eecs.umich.edu elif options.maxtime: 2724167Sbinkertn@umich.edu simtime = m5.ticks.seconds(simtime) 2733395Shsul@eecs.umich.edu print "simulating for: ", simtime 2743395Shsul@eecs.umich.edu maxtick = simtime 2753395Shsul@eecs.umich.edu else: 2763511Shsul@eecs.umich.edu maxtick = m5.MaxTick 2773395Shsul@eecs.umich.edu 2783395Shsul@eecs.umich.edu if options.checkpoint_dir: 2793395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 2805211Ssaidi@eecs.umich.edu elif m5.options.outdir: 2815211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 2823395Shsul@eecs.umich.edu else: 2833395Shsul@eecs.umich.edu cptdir = getcwd() 2843395Shsul@eecs.umich.edu 2855370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 2866654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 2875370Ssaidi@eecs.umich.edu 2885371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 2896654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 2905370Ssaidi@eecs.umich.edu 2919151Satgutier@umich.edu if options.standard_switch and options.repeat_switch: 2929151Satgutier@umich.edu fatal("Can't specify both --standard-switch and --repeat-switch") 2939151Satgutier@umich.edu 2949151Satgutier@umich.edu if options.repeat_switch and options.take_checkpoints: 2959151Satgutier@umich.edu fatal("Can't specify both --repeat-switch and --take-checkpoints") 2969151Satgutier@umich.edu 2973395Shsul@eecs.umich.edu np = options.num_cpus 2983481Shsul@eecs.umich.edu switch_cpus = None 2993481Shsul@eecs.umich.edu 3008318Sksewell@umich.edu if options.prog_interval: 3016144Sksewell@umich.edu for i in xrange(np): 3028311Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_interval 3036144Sksewell@umich.edu 3046641Sksewell@umich.edu if options.maxinsts: 3056641Sksewell@umich.edu for i in xrange(np): 3066641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 3076641Sksewell@umich.edu 3083481Shsul@eecs.umich.edu if cpu_class: 3099433SAndreas.Sandberg@ARM.com switch_cpus = [cpu_class(switched_out=True, cpu_id=(i)) 3103481Shsul@eecs.umich.edu for i in xrange(np)] 3113481Shsul@eecs.umich.edu 3123481Shsul@eecs.umich.edu for i in xrange(np): 3135361Srstrong@cs.ucsd.edu if options.fast_forward: 3145369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 3153481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 3168803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 3179129Sandreas.hansson@arm.com switch_cpus[i].clock = testsys.cpu[i].clock 3185369Ssaidi@eecs.umich.edu # simulation period 3198311Sksewell@umich.edu if options.maxinsts: 3208311Sksewell@umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 3218887Sgeoffrey.blake@arm.com # Add checker cpu if selected 3228887Sgeoffrey.blake@arm.com if options.checker: 3238887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 3243481Shsul@eecs.umich.edu 3255311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 3263481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 3273395Shsul@eecs.umich.edu 3289151Satgutier@umich.edu if options.repeat_switch: 3299518SAndreas.Sandberg@ARM.com switch_class = getCPUClass(options.cpu_type)[0] 3309518SAndreas.Sandberg@ARM.com if switch_class.require_caches() and \ 3319518SAndreas.Sandberg@ARM.com not options.caches: 3329518SAndreas.Sandberg@ARM.com print "%s: Must be used with caches" % str(switch_class) 3339518SAndreas.Sandberg@ARM.com sys.exit(1) 3349518SAndreas.Sandberg@ARM.com if not switch_class.support_take_over(): 3359518SAndreas.Sandberg@ARM.com print "%s: CPU switching not supported" % str(switch_class) 3369518SAndreas.Sandberg@ARM.com sys.exit(1) 3379151Satgutier@umich.edu 3389518SAndreas.Sandberg@ARM.com repeat_switch_cpus = [switch_class(switched_out=True, \ 3399518SAndreas.Sandberg@ARM.com cpu_id=(i)) for i in xrange(np)] 3409151Satgutier@umich.edu 3419151Satgutier@umich.edu for i in xrange(np): 3429151Satgutier@umich.edu repeat_switch_cpus[i].system = testsys 3439151Satgutier@umich.edu repeat_switch_cpus[i].workload = testsys.cpu[i].workload 3449151Satgutier@umich.edu repeat_switch_cpus[i].clock = testsys.cpu[i].clock 3459151Satgutier@umich.edu 3469151Satgutier@umich.edu if options.maxinsts: 3479151Satgutier@umich.edu repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts 3489151Satgutier@umich.edu 3499151Satgutier@umich.edu if options.checker: 3509151Satgutier@umich.edu repeat_switch_cpus[i].addCheckerCpu() 3519151Satgutier@umich.edu 3529151Satgutier@umich.edu testsys.repeat_switch_cpus = repeat_switch_cpus 3539151Satgutier@umich.edu 3549151Satgutier@umich.edu if cpu_class: 3559151Satgutier@umich.edu repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) 3569151Satgutier@umich.edu for i in xrange(np)] 3579151Satgutier@umich.edu else: 3589151Satgutier@umich.edu repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) 3599151Satgutier@umich.edu for i in xrange(np)] 3609151Satgutier@umich.edu 3613395Shsul@eecs.umich.edu if options.standard_switch: 3629433SAndreas.Sandberg@ARM.com switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i)) 3633395Shsul@eecs.umich.edu for i in xrange(np)] 3649433SAndreas.Sandberg@ARM.com switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i)) 3653395Shsul@eecs.umich.edu for i in xrange(np)] 3663478Shsul@eecs.umich.edu 3673395Shsul@eecs.umich.edu for i in xrange(np): 3683395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 3693478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 3708803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 3718803Sgblack@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 3729129Sandreas.hansson@arm.com switch_cpus[i].clock = testsys.cpu[i].clock 3739129Sandreas.hansson@arm.com switch_cpus_1[i].clock = testsys.cpu[i].clock 3743480Shsul@eecs.umich.edu 3755361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 3765369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 3775361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 3785361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 3795361Srstrong@cs.ucsd.edu elif options.fast_forward: 3805369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 3815361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 3825361Srstrong@cs.ucsd.edu elif options.simpoint: 3835378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 3846654Snate@binkert.org fatal('simpoint not found') 3855361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 3865361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 3875361Srstrong@cs.ucsd.edu # No distance specified, just switch 3885361Srstrong@cs.ucsd.edu else: 3895361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 3905361Srstrong@cs.ucsd.edu 3915361Srstrong@cs.ucsd.edu # warmup period 3925361Srstrong@cs.ucsd.edu if options.warmup_insts: 3935361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 3945361Srstrong@cs.ucsd.edu 3955361Srstrong@cs.ucsd.edu # simulation period 3968311Sksewell@umich.edu if options.maxinsts: 3978311Sksewell@umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 3985353Svilas.sridharan@gmail.com 3998887Sgeoffrey.blake@arm.com # attach the checker cpu if selected 4008887Sgeoffrey.blake@arm.com if options.checker: 4018887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 4028887Sgeoffrey.blake@arm.com switch_cpus_1[i].addCheckerCpu() 4038887Sgeoffrey.blake@arm.com 4048211Satgutier@umich.edu testsys.switch_cpus = switch_cpus 4058211Satgutier@umich.edu testsys.switch_cpus_1 = switch_cpus_1 4068211Satgutier@umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 4078211Satgutier@umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 4083395Shsul@eecs.umich.edu 4095361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 4105369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 4115361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 4125361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 4135361Srstrong@cs.ucsd.edu # Set an instruction break point 4145361Srstrong@cs.ucsd.edu if options.simpoint: 4155361Srstrong@cs.ucsd.edu for i in xrange(np): 4165378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 4176654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 4185369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 4195361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 4205361Srstrong@cs.ucsd.edu # used for output below 4215361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 4225361Srstrong@cs.ucsd.edu else: 4235361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 4245361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 4255361Srstrong@cs.ucsd.edu # for the upcoming simulation 4265361Srstrong@cs.ucsd.edu for i in xrange(np): 4275361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 4285361Srstrong@cs.ucsd.edu 4297531Ssteve.reinhardt@amd.com checkpoint_dir = None 4305369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 4319140Snilay@cs.wisc.edu maxtick, checkpoint_dir = findCptDir(options, maxtick, cptdir, testsys) 4327531Ssteve.reinhardt@amd.com m5.instantiate(checkpoint_dir) 4333395Shsul@eecs.umich.edu 4343481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 4355361Srstrong@cs.ucsd.edu if options.standard_switch: 4365361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 4375361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 4385361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4395361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 4405361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 4415361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 4425361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4435361Srstrong@cs.ucsd.edu else: 4445361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 4455361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 4467766Sgblack@eecs.umich.edu print "Switched CPUS @ tick %s" % (m5.curTick()) 4473395Shsul@eecs.umich.edu 4485361Srstrong@cs.ucsd.edu # when you change to Timing (or Atomic), you halt the system 4495361Srstrong@cs.ucsd.edu # given as argument. When you are finished with the system 4505361Srstrong@cs.ucsd.edu # changes (including switchCpus), you must resume the system 4515361Srstrong@cs.ucsd.edu # manually. You DON'T need to resume after just switching 4525361Srstrong@cs.ucsd.edu # CPUs if you haven't changed anything on the system level. 4533395Shsul@eecs.umich.edu 4543395Shsul@eecs.umich.edu m5.changeToTiming(testsys) 4553395Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list) 4563395Shsul@eecs.umich.edu m5.resume(testsys) 4573395Shsul@eecs.umich.edu 4583481Shsul@eecs.umich.edu if options.standard_switch: 4595361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 4605361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 4615361Srstrong@cs.ucsd.edu 4625361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 4635361Srstrong@cs.ucsd.edu if options.warmup_insts: 4645361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4655361Srstrong@cs.ucsd.edu else: 4669151Satgutier@umich.edu exit_event = m5.simulate(options.standard_switch) 4677766Sgblack@eecs.umich.edu print "Switching CPUS @ tick %s" % (m5.curTick()) 4685361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 4695361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 4709344SAndreas.Sandberg@arm.com m5.drain(testsys) 4713481Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list1) 4725072Ssaidi@eecs.umich.edu m5.resume(testsys) 4733395Shsul@eecs.umich.edu 4747489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 4757489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 4767489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 4777489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 4787489Ssteve.reinhardt@amd.com if options.take_checkpoints and options.checkpoint_restore: 4797489Ssteve.reinhardt@amd.com if m5.options.outdir: 4807489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 4817489Ssteve.reinhardt@amd.com else: 4827489Ssteve.reinhardt@amd.com cptdir = getcwd() 4837489Ssteve.reinhardt@amd.com 4845369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 4859140Snilay@cs.wisc.edu # Checkpoints being taken via the command line at <when> and at 4869140Snilay@cs.wisc.edu # subsequent periods of <period>. Checkpoint instructions 4879140Snilay@cs.wisc.edu # received from the benchmark running are ignored and skipped in 4889140Snilay@cs.wisc.edu # favor of command line checkpoint instructions. 4899215Sandreas.hansson@arm.com exit_cause = scriptCheckpoints(options, maxtick, cptdir) 4909140Snilay@cs.wisc.edu else: 4919151Satgutier@umich.edu if options.fast_forward: 4929151Satgutier@umich.edu m5.stats.reset() 4939151Satgutier@umich.edu print "**** REAL SIMULATION ****" 4949151Satgutier@umich.edu 4959140Snilay@cs.wisc.edu # If checkpoints are being taken, then the checkpoint instruction 4969140Snilay@cs.wisc.edu # will occur in the benchmark code it self. 4979151Satgutier@umich.edu if options.repeat_switch and maxtick > options.repeat_switch: 4989460Ssaidi@eecs.umich.edu exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, 4999151Satgutier@umich.edu maxtick, options.repeat_switch) 5009151Satgutier@umich.edu else: 5019460Ssaidi@eecs.umich.edu exit_event = benchCheckpoints(options, maxtick, cptdir) 5023395Shsul@eecs.umich.edu 5039460Ssaidi@eecs.umich.edu print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) 5046776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 5057525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 5069457Svilanova@ac.upc.edu 5079494Sandreas@sandberg.pp.se if not m5.options.interactive: 5089494Sandreas@sandberg.pp.se sys.exit(exit_event.getCode()) 509