Simulation.py revision 9457
15347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan
27534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc.
33395Shsul@eecs.umich.edu# All rights reserved.
43395Shsul@eecs.umich.edu#
53395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
63395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are
73395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright
83395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
93395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
103395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
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133395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from
143395Shsul@eecs.umich.edu# this software without specific prior written permission.
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183395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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273395Shsul@eecs.umich.edu#
283395Shsul@eecs.umich.edu# Authors: Lisa Hsu
293395Shsul@eecs.umich.edu
309457Svilanova@ac.upc.eduimport sys
313395Shsul@eecs.umich.edufrom os import getcwd
323509Shsul@eecs.umich.edufrom os.path import join as joinpath
336654Snate@binkert.org
343395Shsul@eecs.umich.eduimport m5
356654Snate@binkert.orgfrom m5.defines import buildEnv
363395Shsul@eecs.umich.edufrom m5.objects import *
376654Snate@binkert.orgfrom m5.util import *
388724Srdreslin@umich.edufrom O3_ARM_v7a import *
396654Snate@binkert.org
406654Snate@binkert.orgaddToPath('../common')
413395Shsul@eecs.umich.edu
429139Snilay@cs.wisc.edudef getCPUClass(cpu_type):
439139Snilay@cs.wisc.edu    """Returns the required cpu class and the mode of operation.
449139Snilay@cs.wisc.edu    """
459139Snilay@cs.wisc.edu
469139Snilay@cs.wisc.edu    if cpu_type == "timing":
479139Snilay@cs.wisc.edu        return TimingSimpleCPU, 'timing'
489139Snilay@cs.wisc.edu    elif cpu_type == "detailed":
499139Snilay@cs.wisc.edu        return DerivO3CPU, 'timing'
509139Snilay@cs.wisc.edu    elif cpu_type == "arm_detailed":
519139Snilay@cs.wisc.edu        return O3_ARM_v7a_3, 'timing'
529139Snilay@cs.wisc.edu    elif cpu_type == "inorder":
539139Snilay@cs.wisc.edu        return InOrderCPU, 'timing'
549139Snilay@cs.wisc.edu    else:
559139Snilay@cs.wisc.edu        return AtomicSimpleCPU, 'atomic'
569139Snilay@cs.wisc.edu
573481Shsul@eecs.umich.edudef setCPUClass(options):
589139Snilay@cs.wisc.edu    """Returns two cpu classes and the initial mode of operation.
593481Shsul@eecs.umich.edu
609139Snilay@cs.wisc.edu       Restoring from a checkpoint or fast forwarding through a benchmark
619139Snilay@cs.wisc.edu       can be done using one type of cpu, and then the actual
629139Snilay@cs.wisc.edu       simulation can be carried out using another type. This function
639139Snilay@cs.wisc.edu       returns these two types of cpus and the initial mode of operation
649139Snilay@cs.wisc.edu       depending on the options provided.
659139Snilay@cs.wisc.edu    """
669139Snilay@cs.wisc.edu
679139Snilay@cs.wisc.edu    if options.cpu_type == "detailed" or \
689139Snilay@cs.wisc.edu       options.cpu_type == "arm_detailed" or \
699139Snilay@cs.wisc.edu       options.cpu_type == "inorder" :
708718Snilay@cs.wisc.edu        if not options.caches and not options.ruby:
719139Snilay@cs.wisc.edu            fatal("O3/Inorder CPU must be used with caches")
723481Shsul@eecs.umich.edu
739139Snilay@cs.wisc.edu    TmpClass, test_mem_mode = getCPUClass(options.cpu_type)
743481Shsul@eecs.umich.edu    CPUClass = None
753481Shsul@eecs.umich.edu
769139Snilay@cs.wisc.edu    if options.checkpoint_restore != None:
779139Snilay@cs.wisc.edu        if options.restore_with_cpu != options.cpu_type:
783481Shsul@eecs.umich.edu            CPUClass = TmpClass
799139Snilay@cs.wisc.edu            TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu)
809139Snilay@cs.wisc.edu    elif options.fast_forward:
819139Snilay@cs.wisc.edu        CPUClass = TmpClass
829139Snilay@cs.wisc.edu        TmpClass = AtomicSimpleCPU
839139Snilay@cs.wisc.edu        test_mem_mode = 'atomic'
843481Shsul@eecs.umich.edu
853481Shsul@eecs.umich.edu    return (TmpClass, test_mem_mode, CPUClass)
863481Shsul@eecs.umich.edu
878919Snilay@cs.wisc.edudef setWorkCountOptions(system, options):
888919Snilay@cs.wisc.edu    if options.work_item_id != None:
898919Snilay@cs.wisc.edu        system.work_item_id = options.work_item_id
908919Snilay@cs.wisc.edu    if options.work_begin_cpu_id_exit != None:
918919Snilay@cs.wisc.edu        system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
928919Snilay@cs.wisc.edu    if options.work_end_exit_count != None:
938919Snilay@cs.wisc.edu        system.work_end_exit_count = options.work_end_exit_count
948919Snilay@cs.wisc.edu    if options.work_end_checkpoint_count != None:
958919Snilay@cs.wisc.edu        system.work_end_ckpt_count = options.work_end_checkpoint_count
968919Snilay@cs.wisc.edu    if options.work_begin_exit_count != None:
978919Snilay@cs.wisc.edu        system.work_begin_exit_count = options.work_begin_exit_count
988919Snilay@cs.wisc.edu    if options.work_begin_checkpoint_count != None:
998919Snilay@cs.wisc.edu        system.work_begin_ckpt_count = options.work_begin_checkpoint_count
1008919Snilay@cs.wisc.edu    if options.work_cpus_checkpoint_count != None:
1018919Snilay@cs.wisc.edu        system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
1023481Shsul@eecs.umich.edu
1039140Snilay@cs.wisc.edudef findCptDir(options, maxtick, cptdir, testsys):
1049140Snilay@cs.wisc.edu    """Figures out the directory from which the checkpointed state is read.
1059140Snilay@cs.wisc.edu
1069140Snilay@cs.wisc.edu    There are two different ways in which the directories holding checkpoints
1079140Snilay@cs.wisc.edu    can be named --
1089140Snilay@cs.wisc.edu    1. cpt.<benchmark name>.<instruction count when the checkpoint was taken>
1099140Snilay@cs.wisc.edu    2. cpt.<some number, usually the tick value when the checkpoint was taken>
1109140Snilay@cs.wisc.edu
1119140Snilay@cs.wisc.edu    This function parses through the options to figure out which one of the
1129140Snilay@cs.wisc.edu    above should be used for selecting the checkpoint, and then figures out
1139140Snilay@cs.wisc.edu    the appropriate directory.
1149140Snilay@cs.wisc.edu
1159140Snilay@cs.wisc.edu    It also sets the value of the maximum tick value till which the simulation
1169140Snilay@cs.wisc.edu    will run.
1179140Snilay@cs.wisc.edu    """
1189140Snilay@cs.wisc.edu
1199140Snilay@cs.wisc.edu    from os.path import isdir, exists
1209140Snilay@cs.wisc.edu    from os import listdir
1219140Snilay@cs.wisc.edu    import re
1229140Snilay@cs.wisc.edu
1239140Snilay@cs.wisc.edu    if not isdir(cptdir):
1249140Snilay@cs.wisc.edu        fatal("checkpoint dir %s does not exist!", cptdir)
1259140Snilay@cs.wisc.edu
1269140Snilay@cs.wisc.edu    if options.at_instruction or options.simpoint:
1279140Snilay@cs.wisc.edu        inst = options.checkpoint_restore
1289140Snilay@cs.wisc.edu        if options.simpoint:
1299140Snilay@cs.wisc.edu            # assume workload 0 has the simpoint
1309140Snilay@cs.wisc.edu            if testsys.cpu[0].workload[0].simpoint == 0:
1319140Snilay@cs.wisc.edu                fatal('Unable to find simpoint')
1329140Snilay@cs.wisc.edu            inst += int(testsys.cpu[0].workload[0].simpoint)
1339140Snilay@cs.wisc.edu
1349140Snilay@cs.wisc.edu        checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst))
1359140Snilay@cs.wisc.edu        if not exists(checkpoint_dir):
1369140Snilay@cs.wisc.edu            fatal("Unable to find checkpoint directory %s", checkpoint_dir)
1379140Snilay@cs.wisc.edu    else:
1389140Snilay@cs.wisc.edu        dirs = listdir(cptdir)
1399140Snilay@cs.wisc.edu        expr = re.compile('cpt\.([0-9]*)')
1409140Snilay@cs.wisc.edu        cpts = []
1419140Snilay@cs.wisc.edu        for dir in dirs:
1429140Snilay@cs.wisc.edu            match = expr.match(dir)
1439140Snilay@cs.wisc.edu            if match:
1449140Snilay@cs.wisc.edu                cpts.append(match.group(1))
1459140Snilay@cs.wisc.edu
1469140Snilay@cs.wisc.edu        cpts.sort(lambda a,b: cmp(long(a), long(b)))
1479140Snilay@cs.wisc.edu
1489140Snilay@cs.wisc.edu        cpt_num = options.checkpoint_restore
1499140Snilay@cs.wisc.edu        if cpt_num > len(cpts):
1509140Snilay@cs.wisc.edu            fatal('Checkpoint %d not found', cpt_num)
1519140Snilay@cs.wisc.edu
1529140Snilay@cs.wisc.edu        maxtick = maxtick - int(cpts[cpt_num - 1])
1539140Snilay@cs.wisc.edu        checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1])
1549140Snilay@cs.wisc.edu
1559140Snilay@cs.wisc.edu    return maxtick, checkpoint_dir
1569140Snilay@cs.wisc.edu
1579215Sandreas.hansson@arm.comdef scriptCheckpoints(options, maxtick, cptdir):
1589140Snilay@cs.wisc.edu    if options.at_instruction or options.simpoint:
1599140Snilay@cs.wisc.edu        checkpoint_inst = int(options.take_checkpoints)
1609140Snilay@cs.wisc.edu
1619140Snilay@cs.wisc.edu        # maintain correct offset if we restored from some instruction
1629140Snilay@cs.wisc.edu        if options.checkpoint_restore != None:
1639140Snilay@cs.wisc.edu            checkpoint_inst += options.checkpoint_restore
1649140Snilay@cs.wisc.edu
1659140Snilay@cs.wisc.edu        print "Creating checkpoint at inst:%d" % (checkpoint_inst)
1669140Snilay@cs.wisc.edu        exit_event = m5.simulate()
1679140Snilay@cs.wisc.edu        exit_cause = exit_event.getCause()
1689140Snilay@cs.wisc.edu        print "exit cause = %s" % exit_cause
1699140Snilay@cs.wisc.edu
1709140Snilay@cs.wisc.edu        # skip checkpoint instructions should they exist
1719140Snilay@cs.wisc.edu        while exit_cause == "checkpoint":
1729140Snilay@cs.wisc.edu            exit_event = m5.simulate()
1739140Snilay@cs.wisc.edu            exit_cause = exit_event.getCause()
1749140Snilay@cs.wisc.edu
1759140Snilay@cs.wisc.edu        if exit_cause == "a thread reached the max instruction count":
1769140Snilay@cs.wisc.edu            m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \
1779140Snilay@cs.wisc.edu                    (options.bench, checkpoint_inst)))
1789140Snilay@cs.wisc.edu            print "Checkpoint written."
1799140Snilay@cs.wisc.edu
1809140Snilay@cs.wisc.edu    else:
1819140Snilay@cs.wisc.edu        when, period = options.take_checkpoints.split(",", 1)
1829140Snilay@cs.wisc.edu        when = int(when)
1839140Snilay@cs.wisc.edu        period = int(period)
1849156Sandreas.hansson@arm.com        num_checkpoints = 0
1859140Snilay@cs.wisc.edu
1869140Snilay@cs.wisc.edu        exit_event = m5.simulate(when)
1879140Snilay@cs.wisc.edu        exit_cause = exit_event.getCause()
1889140Snilay@cs.wisc.edu        while exit_cause == "checkpoint":
1899140Snilay@cs.wisc.edu            exit_event = m5.simulate(when - m5.curTick())
1909140Snilay@cs.wisc.edu            exit_cause = exit_event.getCause()
1919140Snilay@cs.wisc.edu
1929140Snilay@cs.wisc.edu        if exit_cause == "simulate() limit reached":
1939140Snilay@cs.wisc.edu            m5.checkpoint(joinpath(cptdir, "cpt.%d"))
1949140Snilay@cs.wisc.edu            num_checkpoints += 1
1959140Snilay@cs.wisc.edu
1969140Snilay@cs.wisc.edu        sim_ticks = when
1979140Snilay@cs.wisc.edu        max_checkpoints = options.max_checkpoints
1989140Snilay@cs.wisc.edu
1999140Snilay@cs.wisc.edu        while num_checkpoints < max_checkpoints and \
2009140Snilay@cs.wisc.edu                exit_cause == "simulate() limit reached":
2019140Snilay@cs.wisc.edu            if (sim_ticks + period) > maxtick:
2029140Snilay@cs.wisc.edu                exit_event = m5.simulate(maxtick - sim_ticks)
2039140Snilay@cs.wisc.edu                exit_cause = exit_event.getCause()
2049140Snilay@cs.wisc.edu                break
2059140Snilay@cs.wisc.edu            else:
2069140Snilay@cs.wisc.edu                exit_event = m5.simulate(period)
2079140Snilay@cs.wisc.edu                exit_cause = exit_event.getCause()
2089140Snilay@cs.wisc.edu                sim_ticks += period
2099140Snilay@cs.wisc.edu                while exit_event.getCause() == "checkpoint":
2109140Snilay@cs.wisc.edu                    exit_event = m5.simulate(sim_ticks - m5.curTick())
2119140Snilay@cs.wisc.edu                if exit_event.getCause() == "simulate() limit reached":
2129140Snilay@cs.wisc.edu                    m5.checkpoint(joinpath(cptdir, "cpt.%d"))
2139140Snilay@cs.wisc.edu                    num_checkpoints += 1
2149140Snilay@cs.wisc.edu
2159140Snilay@cs.wisc.edu    return exit_cause
2169140Snilay@cs.wisc.edu
2179140Snilay@cs.wisc.edudef benchCheckpoints(options, maxtick, cptdir):
2189140Snilay@cs.wisc.edu    exit_event = m5.simulate(maxtick)
2199140Snilay@cs.wisc.edu    exit_cause = exit_event.getCause()
2209140Snilay@cs.wisc.edu
2219140Snilay@cs.wisc.edu    num_checkpoints = 0
2229140Snilay@cs.wisc.edu    max_checkpoints = options.max_checkpoints
2239140Snilay@cs.wisc.edu
2249140Snilay@cs.wisc.edu    while exit_cause == "checkpoint":
2259140Snilay@cs.wisc.edu        m5.checkpoint(joinpath(cptdir, "cpt.%d"))
2269140Snilay@cs.wisc.edu        num_checkpoints += 1
2279140Snilay@cs.wisc.edu        if num_checkpoints == max_checkpoints:
2289140Snilay@cs.wisc.edu            exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
2299140Snilay@cs.wisc.edu            break
2309140Snilay@cs.wisc.edu
2319140Snilay@cs.wisc.edu        exit_event = m5.simulate(maxtick - m5.curTick())
2329140Snilay@cs.wisc.edu        exit_cause = exit_event.getCause()
2339140Snilay@cs.wisc.edu
2349140Snilay@cs.wisc.edu    return exit_cause
2359140Snilay@cs.wisc.edu
2369151Satgutier@umich.edudef repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, switch_freq):
2379151Satgutier@umich.edu    print "starting switch loop"
2389151Satgutier@umich.edu    while True:
2399151Satgutier@umich.edu        exit_event = m5.simulate(switch_freq)
2409151Satgutier@umich.edu        exit_cause = exit_event.getCause()
2419151Satgutier@umich.edu
2429151Satgutier@umich.edu        if exit_cause != "simulate() limit reached":
2439151Satgutier@umich.edu            return exit_cause
2449151Satgutier@umich.edu
2459151Satgutier@umich.edu        print "draining the system"
2469344SAndreas.Sandberg@arm.com        m5.drain(testsys)
2479151Satgutier@umich.edu        m5.switchCpus(repeat_switch_cpu_list)
2489151Satgutier@umich.edu        m5.resume(testsys)
2499151Satgutier@umich.edu
2509151Satgutier@umich.edu        tmp_cpu_list = []
2519151Satgutier@umich.edu        for old_cpu, new_cpu in repeat_switch_cpu_list:
2529151Satgutier@umich.edu            tmp_cpu_list.append((new_cpu, old_cpu))
2539151Satgutier@umich.edu        repeat_switch_cpu_list = tmp_cpu_list
2549151Satgutier@umich.edu
2559151Satgutier@umich.edu        if (maxtick - m5.curTick()) <= switch_freq:
2569151Satgutier@umich.edu            exit_event = m5.simulate(maxtick - m5.curTick())
2579151Satgutier@umich.edu            return exit_event.getCause()
2589151Satgutier@umich.edu
2593481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class):
2603395Shsul@eecs.umich.edu    if options.maxtick:
2613395Shsul@eecs.umich.edu        maxtick = options.maxtick
2623395Shsul@eecs.umich.edu    elif options.maxtime:
2634167Sbinkertn@umich.edu        simtime = m5.ticks.seconds(simtime)
2643395Shsul@eecs.umich.edu        print "simulating for: ", simtime
2653395Shsul@eecs.umich.edu        maxtick = simtime
2663395Shsul@eecs.umich.edu    else:
2673511Shsul@eecs.umich.edu        maxtick = m5.MaxTick
2683395Shsul@eecs.umich.edu
2693395Shsul@eecs.umich.edu    if options.checkpoint_dir:
2703395Shsul@eecs.umich.edu        cptdir = options.checkpoint_dir
2715211Ssaidi@eecs.umich.edu    elif m5.options.outdir:
2725211Ssaidi@eecs.umich.edu        cptdir = m5.options.outdir
2733395Shsul@eecs.umich.edu    else:
2743395Shsul@eecs.umich.edu        cptdir = getcwd()
2753395Shsul@eecs.umich.edu
2765370Ssaidi@eecs.umich.edu    if options.fast_forward and options.checkpoint_restore != None:
2776654Snate@binkert.org        fatal("Can't specify both --fast-forward and --checkpoint-restore")
2785370Ssaidi@eecs.umich.edu
2795371Shsul@eecs.umich.edu    if options.standard_switch and not options.caches:
2806654Snate@binkert.org        fatal("Must specify --caches when using --standard-switch")
2815370Ssaidi@eecs.umich.edu
2829151Satgutier@umich.edu    if options.standard_switch and options.repeat_switch:
2839151Satgutier@umich.edu        fatal("Can't specify both --standard-switch and --repeat-switch")
2849151Satgutier@umich.edu
2859151Satgutier@umich.edu    if options.repeat_switch and options.take_checkpoints:
2869151Satgutier@umich.edu        fatal("Can't specify both --repeat-switch and --take-checkpoints")
2879151Satgutier@umich.edu
2883395Shsul@eecs.umich.edu    np = options.num_cpus
2893481Shsul@eecs.umich.edu    switch_cpus = None
2903481Shsul@eecs.umich.edu
2918318Sksewell@umich.edu    if options.prog_interval:
2926144Sksewell@umich.edu        for i in xrange(np):
2938311Sksewell@umich.edu            testsys.cpu[i].progress_interval = options.prog_interval
2946144Sksewell@umich.edu
2956641Sksewell@umich.edu    if options.maxinsts:
2966641Sksewell@umich.edu        for i in xrange(np):
2976641Sksewell@umich.edu            testsys.cpu[i].max_insts_any_thread = options.maxinsts
2986641Sksewell@umich.edu
2993481Shsul@eecs.umich.edu    if cpu_class:
3009433SAndreas.Sandberg@ARM.com        switch_cpus = [cpu_class(switched_out=True, cpu_id=(i))
3013481Shsul@eecs.umich.edu                       for i in xrange(np)]
3023481Shsul@eecs.umich.edu
3033481Shsul@eecs.umich.edu        for i in xrange(np):
3045361Srstrong@cs.ucsd.edu            if options.fast_forward:
3055369Ssaidi@eecs.umich.edu                testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
3063481Shsul@eecs.umich.edu            switch_cpus[i].system =  testsys
3078803Sgblack@eecs.umich.edu            switch_cpus[i].workload = testsys.cpu[i].workload
3089129Sandreas.hansson@arm.com            switch_cpus[i].clock = testsys.cpu[i].clock
3095369Ssaidi@eecs.umich.edu            # simulation period
3108311Sksewell@umich.edu            if options.maxinsts:
3118311Sksewell@umich.edu                switch_cpus[i].max_insts_any_thread = options.maxinsts
3128887Sgeoffrey.blake@arm.com            # Add checker cpu if selected
3138887Sgeoffrey.blake@arm.com            if options.checker:
3148887Sgeoffrey.blake@arm.com                switch_cpus[i].addCheckerCpu()
3153481Shsul@eecs.umich.edu
3165311Ssaidi@eecs.umich.edu        testsys.switch_cpus = switch_cpus
3173481Shsul@eecs.umich.edu        switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
3183395Shsul@eecs.umich.edu
3199151Satgutier@umich.edu    if options.repeat_switch:
3209151Satgutier@umich.edu        if options.cpu_type == "arm_detailed":
3219151Satgutier@umich.edu            if not options.caches:
3229151Satgutier@umich.edu                print "O3 CPU must be used with caches"
3239151Satgutier@umich.edu                sys.exit(1)
3249151Satgutier@umich.edu
3259433SAndreas.Sandberg@ARM.com            repeat_switch_cpus = [O3_ARM_v7a_3(switched_out=True, \
3269151Satgutier@umich.edu                                  cpu_id=(i)) for i in xrange(np)]
3279151Satgutier@umich.edu        elif options.cpu_type == "detailed":
3289151Satgutier@umich.edu            if not options.caches:
3299151Satgutier@umich.edu                print "O3 CPU must be used with caches"
3309151Satgutier@umich.edu                sys.exit(1)
3319151Satgutier@umich.edu
3329433SAndreas.Sandberg@ARM.com            repeat_switch_cpus = [DerivO3CPU(switched_out=True, \
3339151Satgutier@umich.edu                                  cpu_id=(i)) for i in xrange(np)]
3349151Satgutier@umich.edu        elif options.cpu_type == "inorder":
3359151Satgutier@umich.edu            print "inorder CPU switching not supported"
3369151Satgutier@umich.edu            sys.exit(1)
3379151Satgutier@umich.edu        elif options.cpu_type == "timing":
3389433SAndreas.Sandberg@ARM.com            repeat_switch_cpus = [TimingSimpleCPU(switched_out=True, \
3399151Satgutier@umich.edu                                  cpu_id=(i)) for i in xrange(np)]
3409151Satgutier@umich.edu        else:
3419433SAndreas.Sandberg@ARM.com            repeat_switch_cpus = [AtomicSimpleCPU(switched_out=True, \
3429151Satgutier@umich.edu                                  cpu_id=(i)) for i in xrange(np)]
3439151Satgutier@umich.edu
3449151Satgutier@umich.edu        for i in xrange(np):
3459151Satgutier@umich.edu            repeat_switch_cpus[i].system = testsys
3469151Satgutier@umich.edu            repeat_switch_cpus[i].workload = testsys.cpu[i].workload
3479151Satgutier@umich.edu            repeat_switch_cpus[i].clock = testsys.cpu[i].clock
3489151Satgutier@umich.edu
3499151Satgutier@umich.edu            if options.maxinsts:
3509151Satgutier@umich.edu                repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts
3519151Satgutier@umich.edu
3529151Satgutier@umich.edu            if options.checker:
3539151Satgutier@umich.edu                repeat_switch_cpus[i].addCheckerCpu()
3549151Satgutier@umich.edu
3559151Satgutier@umich.edu        testsys.repeat_switch_cpus = repeat_switch_cpus
3569151Satgutier@umich.edu
3579151Satgutier@umich.edu        if cpu_class:
3589151Satgutier@umich.edu            repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i])
3599151Satgutier@umich.edu                                      for i in xrange(np)]
3609151Satgutier@umich.edu        else:
3619151Satgutier@umich.edu            repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i])
3629151Satgutier@umich.edu                                      for i in xrange(np)]
3639151Satgutier@umich.edu
3643395Shsul@eecs.umich.edu    if options.standard_switch:
3659433SAndreas.Sandberg@ARM.com        switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i))
3663395Shsul@eecs.umich.edu                       for i in xrange(np)]
3679433SAndreas.Sandberg@ARM.com        switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i))
3683395Shsul@eecs.umich.edu                        for i in xrange(np)]
3693478Shsul@eecs.umich.edu
3703395Shsul@eecs.umich.edu        for i in xrange(np):
3713395Shsul@eecs.umich.edu            switch_cpus[i].system =  testsys
3723478Shsul@eecs.umich.edu            switch_cpus_1[i].system =  testsys
3738803Sgblack@eecs.umich.edu            switch_cpus[i].workload = testsys.cpu[i].workload
3748803Sgblack@eecs.umich.edu            switch_cpus_1[i].workload = testsys.cpu[i].workload
3759129Sandreas.hansson@arm.com            switch_cpus[i].clock = testsys.cpu[i].clock
3769129Sandreas.hansson@arm.com            switch_cpus_1[i].clock = testsys.cpu[i].clock
3773480Shsul@eecs.umich.edu
3785361Srstrong@cs.ucsd.edu            # if restoring, make atomic cpu simulate only a few instructions
3795369Ssaidi@eecs.umich.edu            if options.checkpoint_restore != None:
3805361Srstrong@cs.ucsd.edu                testsys.cpu[i].max_insts_any_thread = 1
3815361Srstrong@cs.ucsd.edu            # Fast forward to specified location if we are not restoring
3825361Srstrong@cs.ucsd.edu            elif options.fast_forward:
3835369Ssaidi@eecs.umich.edu                testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
3845361Srstrong@cs.ucsd.edu            # Fast forward to a simpoint (warning: time consuming)
3855361Srstrong@cs.ucsd.edu            elif options.simpoint:
3865378Ssaidi@eecs.umich.edu                if testsys.cpu[i].workload[0].simpoint == 0:
3876654Snate@binkert.org                    fatal('simpoint not found')
3885361Srstrong@cs.ucsd.edu                testsys.cpu[i].max_insts_any_thread = \
3895361Srstrong@cs.ucsd.edu                    testsys.cpu[i].workload[0].simpoint
3905361Srstrong@cs.ucsd.edu            # No distance specified, just switch
3915361Srstrong@cs.ucsd.edu            else:
3925361Srstrong@cs.ucsd.edu                testsys.cpu[i].max_insts_any_thread = 1
3935361Srstrong@cs.ucsd.edu
3945361Srstrong@cs.ucsd.edu            # warmup period
3955361Srstrong@cs.ucsd.edu            if options.warmup_insts:
3965361Srstrong@cs.ucsd.edu                switch_cpus[i].max_insts_any_thread =  options.warmup_insts
3975361Srstrong@cs.ucsd.edu
3985361Srstrong@cs.ucsd.edu            # simulation period
3998311Sksewell@umich.edu            if options.maxinsts:
4008311Sksewell@umich.edu                switch_cpus_1[i].max_insts_any_thread = options.maxinsts
4015353Svilas.sridharan@gmail.com
4028887Sgeoffrey.blake@arm.com            # attach the checker cpu if selected
4038887Sgeoffrey.blake@arm.com            if options.checker:
4048887Sgeoffrey.blake@arm.com                switch_cpus[i].addCheckerCpu()
4058887Sgeoffrey.blake@arm.com                switch_cpus_1[i].addCheckerCpu()
4068887Sgeoffrey.blake@arm.com
4078211Satgutier@umich.edu        testsys.switch_cpus = switch_cpus
4088211Satgutier@umich.edu        testsys.switch_cpus_1 = switch_cpus_1
4098211Satgutier@umich.edu        switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
4108211Satgutier@umich.edu        switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
4113395Shsul@eecs.umich.edu
4125361Srstrong@cs.ucsd.edu    # set the checkpoint in the cpu before m5.instantiate is called
4135369Ssaidi@eecs.umich.edu    if options.take_checkpoints != None and \
4145361Srstrong@cs.ucsd.edu           (options.simpoint or options.at_instruction):
4155361Srstrong@cs.ucsd.edu        offset = int(options.take_checkpoints)
4165361Srstrong@cs.ucsd.edu        # Set an instruction break point
4175361Srstrong@cs.ucsd.edu        if options.simpoint:
4185361Srstrong@cs.ucsd.edu            for i in xrange(np):
4195378Ssaidi@eecs.umich.edu                if testsys.cpu[i].workload[0].simpoint == 0:
4206654Snate@binkert.org                    fatal('no simpoint for testsys.cpu[%d].workload[0]', i)
4215369Ssaidi@eecs.umich.edu                checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset
4225361Srstrong@cs.ucsd.edu                testsys.cpu[i].max_insts_any_thread = checkpoint_inst
4235361Srstrong@cs.ucsd.edu                # used for output below
4245361Srstrong@cs.ucsd.edu                options.take_checkpoints = checkpoint_inst
4255361Srstrong@cs.ucsd.edu        else:
4265361Srstrong@cs.ucsd.edu            options.take_checkpoints = offset
4275361Srstrong@cs.ucsd.edu            # Set all test cpus with the right number of instructions
4285361Srstrong@cs.ucsd.edu            # for the upcoming simulation
4295361Srstrong@cs.ucsd.edu            for i in xrange(np):
4305361Srstrong@cs.ucsd.edu                testsys.cpu[i].max_insts_any_thread = offset
4315361Srstrong@cs.ucsd.edu
4327531Ssteve.reinhardt@amd.com    checkpoint_dir = None
4335369Ssaidi@eecs.umich.edu    if options.checkpoint_restore != None:
4349140Snilay@cs.wisc.edu        maxtick, checkpoint_dir = findCptDir(options, maxtick, cptdir, testsys)
4357531Ssteve.reinhardt@amd.com    m5.instantiate(checkpoint_dir)
4363395Shsul@eecs.umich.edu
4373481Shsul@eecs.umich.edu    if options.standard_switch or cpu_class:
4385361Srstrong@cs.ucsd.edu        if options.standard_switch:
4395361Srstrong@cs.ucsd.edu            print "Switch at instruction count:%s" % \
4405361Srstrong@cs.ucsd.edu                    str(testsys.cpu[0].max_insts_any_thread)
4415361Srstrong@cs.ucsd.edu            exit_event = m5.simulate()
4425361Srstrong@cs.ucsd.edu        elif cpu_class and options.fast_forward:
4435361Srstrong@cs.ucsd.edu            print "Switch at instruction count:%s" % \
4445361Srstrong@cs.ucsd.edu                    str(testsys.cpu[0].max_insts_any_thread)
4455361Srstrong@cs.ucsd.edu            exit_event = m5.simulate()
4465361Srstrong@cs.ucsd.edu        else:
4475361Srstrong@cs.ucsd.edu            print "Switch at curTick count:%s" % str(10000)
4485361Srstrong@cs.ucsd.edu            exit_event = m5.simulate(10000)
4497766Sgblack@eecs.umich.edu        print "Switched CPUS @ tick %s" % (m5.curTick())
4503395Shsul@eecs.umich.edu
4515361Srstrong@cs.ucsd.edu        # when you change to Timing (or Atomic), you halt the system
4525361Srstrong@cs.ucsd.edu        # given as argument.  When you are finished with the system
4535361Srstrong@cs.ucsd.edu        # changes (including switchCpus), you must resume the system
4545361Srstrong@cs.ucsd.edu        # manually.  You DON'T need to resume after just switching
4555361Srstrong@cs.ucsd.edu        # CPUs if you haven't changed anything on the system level.
4563395Shsul@eecs.umich.edu
4573395Shsul@eecs.umich.edu        m5.changeToTiming(testsys)
4583395Shsul@eecs.umich.edu        m5.switchCpus(switch_cpu_list)
4593395Shsul@eecs.umich.edu        m5.resume(testsys)
4603395Shsul@eecs.umich.edu
4613481Shsul@eecs.umich.edu        if options.standard_switch:
4625361Srstrong@cs.ucsd.edu            print "Switch at instruction count:%d" % \
4635361Srstrong@cs.ucsd.edu                    (testsys.switch_cpus[0].max_insts_any_thread)
4645361Srstrong@cs.ucsd.edu
4655361Srstrong@cs.ucsd.edu            #warmup instruction count may have already been set
4665361Srstrong@cs.ucsd.edu            if options.warmup_insts:
4675361Srstrong@cs.ucsd.edu                exit_event = m5.simulate()
4685361Srstrong@cs.ucsd.edu            else:
4699151Satgutier@umich.edu                exit_event = m5.simulate(options.standard_switch)
4707766Sgblack@eecs.umich.edu            print "Switching CPUS @ tick %s" % (m5.curTick())
4715361Srstrong@cs.ucsd.edu            print "Simulation ends instruction count:%d" % \
4725361Srstrong@cs.ucsd.edu                    (testsys.switch_cpus_1[0].max_insts_any_thread)
4739344SAndreas.Sandberg@arm.com            m5.drain(testsys)
4743481Shsul@eecs.umich.edu            m5.switchCpus(switch_cpu_list1)
4755072Ssaidi@eecs.umich.edu            m5.resume(testsys)
4763395Shsul@eecs.umich.edu
4777489Ssteve.reinhardt@amd.com    # If we're taking and restoring checkpoints, use checkpoint_dir
4787489Ssteve.reinhardt@amd.com    # option only for finding the checkpoints to restore from.  This
4797489Ssteve.reinhardt@amd.com    # lets us test checkpointing by restoring from one set of
4807489Ssteve.reinhardt@amd.com    # checkpoints, generating a second set, and then comparing them.
4817489Ssteve.reinhardt@amd.com    if options.take_checkpoints and options.checkpoint_restore:
4827489Ssteve.reinhardt@amd.com        if m5.options.outdir:
4837489Ssteve.reinhardt@amd.com            cptdir = m5.options.outdir
4847489Ssteve.reinhardt@amd.com        else:
4857489Ssteve.reinhardt@amd.com            cptdir = getcwd()
4867489Ssteve.reinhardt@amd.com
4875369Ssaidi@eecs.umich.edu    if options.take_checkpoints != None :
4889140Snilay@cs.wisc.edu        # Checkpoints being taken via the command line at <when> and at
4899140Snilay@cs.wisc.edu        # subsequent periods of <period>.  Checkpoint instructions
4909140Snilay@cs.wisc.edu        # received from the benchmark running are ignored and skipped in
4919140Snilay@cs.wisc.edu        # favor of command line checkpoint instructions.
4929215Sandreas.hansson@arm.com        exit_cause = scriptCheckpoints(options, maxtick, cptdir)
4939140Snilay@cs.wisc.edu    else:
4949151Satgutier@umich.edu        if options.fast_forward:
4959151Satgutier@umich.edu            m5.stats.reset()
4969151Satgutier@umich.edu        print "**** REAL SIMULATION ****"
4979151Satgutier@umich.edu
4989140Snilay@cs.wisc.edu        # If checkpoints are being taken, then the checkpoint instruction
4999140Snilay@cs.wisc.edu        # will occur in the benchmark code it self.
5009151Satgutier@umich.edu        if options.repeat_switch and maxtick > options.repeat_switch:
5019151Satgutier@umich.edu            exit_cause = repeatSwitch(testsys, repeat_switch_cpu_list,
5029151Satgutier@umich.edu                                      maxtick, options.repeat_switch)
5039151Satgutier@umich.edu        else:
5049151Satgutier@umich.edu            exit_cause = benchCheckpoints(options, maxtick, cptdir)
5053395Shsul@eecs.umich.edu
5067766Sgblack@eecs.umich.edu    print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause)
5076776SBrad.Beckmann@amd.com    if options.checkpoint_at_end:
5087525Ssteve.reinhardt@amd.com        m5.checkpoint(joinpath(cptdir, "cpt.%d"))
5099457Svilanova@ac.upc.edu
5109457Svilanova@ac.upc.edu    sys.exit(exit_event.getCode())
511