Simulation.py revision 9215
15347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 27534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 33395Shsul@eecs.umich.edu# All rights reserved. 43395Shsul@eecs.umich.edu# 53395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 63395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 73395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 83395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 93395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 103395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 113395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 123395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 133395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143395Shsul@eecs.umich.edu# this software without specific prior written permission. 153395Shsul@eecs.umich.edu# 163395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# Authors: Lisa Hsu 293395Shsul@eecs.umich.edu 303395Shsul@eecs.umich.edufrom os import getcwd 313509Shsul@eecs.umich.edufrom os.path import join as joinpath 326654Snate@binkert.org 333395Shsul@eecs.umich.eduimport m5 346654Snate@binkert.orgfrom m5.defines import buildEnv 353395Shsul@eecs.umich.edufrom m5.objects import * 366654Snate@binkert.orgfrom m5.util import * 378724Srdreslin@umich.edufrom O3_ARM_v7a import * 386654Snate@binkert.org 396654Snate@binkert.orgaddToPath('../common') 403395Shsul@eecs.umich.edu 419139Snilay@cs.wisc.edudef getCPUClass(cpu_type): 429139Snilay@cs.wisc.edu """Returns the required cpu class and the mode of operation. 439139Snilay@cs.wisc.edu """ 449139Snilay@cs.wisc.edu 459139Snilay@cs.wisc.edu if cpu_type == "timing": 469139Snilay@cs.wisc.edu return TimingSimpleCPU, 'timing' 479139Snilay@cs.wisc.edu elif cpu_type == "detailed": 489139Snilay@cs.wisc.edu return DerivO3CPU, 'timing' 499139Snilay@cs.wisc.edu elif cpu_type == "arm_detailed": 509139Snilay@cs.wisc.edu return O3_ARM_v7a_3, 'timing' 519139Snilay@cs.wisc.edu elif cpu_type == "inorder": 529139Snilay@cs.wisc.edu return InOrderCPU, 'timing' 539139Snilay@cs.wisc.edu else: 549139Snilay@cs.wisc.edu return AtomicSimpleCPU, 'atomic' 559139Snilay@cs.wisc.edu 563481Shsul@eecs.umich.edudef setCPUClass(options): 579139Snilay@cs.wisc.edu """Returns two cpu classes and the initial mode of operation. 583481Shsul@eecs.umich.edu 599139Snilay@cs.wisc.edu Restoring from a checkpoint or fast forwarding through a benchmark 609139Snilay@cs.wisc.edu can be done using one type of cpu, and then the actual 619139Snilay@cs.wisc.edu simulation can be carried out using another type. This function 629139Snilay@cs.wisc.edu returns these two types of cpus and the initial mode of operation 639139Snilay@cs.wisc.edu depending on the options provided. 649139Snilay@cs.wisc.edu """ 659139Snilay@cs.wisc.edu 669139Snilay@cs.wisc.edu if options.cpu_type == "detailed" or \ 679139Snilay@cs.wisc.edu options.cpu_type == "arm_detailed" or \ 689139Snilay@cs.wisc.edu options.cpu_type == "inorder" : 698718Snilay@cs.wisc.edu if not options.caches and not options.ruby: 709139Snilay@cs.wisc.edu fatal("O3/Inorder CPU must be used with caches") 713481Shsul@eecs.umich.edu 729139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.cpu_type) 733481Shsul@eecs.umich.edu CPUClass = None 743481Shsul@eecs.umich.edu 759139Snilay@cs.wisc.edu if options.checkpoint_restore != None: 769139Snilay@cs.wisc.edu if options.restore_with_cpu != options.cpu_type: 773481Shsul@eecs.umich.edu CPUClass = TmpClass 789139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu) 799139Snilay@cs.wisc.edu elif options.fast_forward: 809139Snilay@cs.wisc.edu CPUClass = TmpClass 819139Snilay@cs.wisc.edu TmpClass = AtomicSimpleCPU 829139Snilay@cs.wisc.edu test_mem_mode = 'atomic' 833481Shsul@eecs.umich.edu 843481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 853481Shsul@eecs.umich.edu 868919Snilay@cs.wisc.edudef setWorkCountOptions(system, options): 878919Snilay@cs.wisc.edu if options.work_item_id != None: 888919Snilay@cs.wisc.edu system.work_item_id = options.work_item_id 898919Snilay@cs.wisc.edu if options.work_begin_cpu_id_exit != None: 908919Snilay@cs.wisc.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 918919Snilay@cs.wisc.edu if options.work_end_exit_count != None: 928919Snilay@cs.wisc.edu system.work_end_exit_count = options.work_end_exit_count 938919Snilay@cs.wisc.edu if options.work_end_checkpoint_count != None: 948919Snilay@cs.wisc.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 958919Snilay@cs.wisc.edu if options.work_begin_exit_count != None: 968919Snilay@cs.wisc.edu system.work_begin_exit_count = options.work_begin_exit_count 978919Snilay@cs.wisc.edu if options.work_begin_checkpoint_count != None: 988919Snilay@cs.wisc.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 998919Snilay@cs.wisc.edu if options.work_cpus_checkpoint_count != None: 1008919Snilay@cs.wisc.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 1013481Shsul@eecs.umich.edu 1029140Snilay@cs.wisc.edudef findCptDir(options, maxtick, cptdir, testsys): 1039140Snilay@cs.wisc.edu """Figures out the directory from which the checkpointed state is read. 1049140Snilay@cs.wisc.edu 1059140Snilay@cs.wisc.edu There are two different ways in which the directories holding checkpoints 1069140Snilay@cs.wisc.edu can be named -- 1079140Snilay@cs.wisc.edu 1. cpt.<benchmark name>.<instruction count when the checkpoint was taken> 1089140Snilay@cs.wisc.edu 2. cpt.<some number, usually the tick value when the checkpoint was taken> 1099140Snilay@cs.wisc.edu 1109140Snilay@cs.wisc.edu This function parses through the options to figure out which one of the 1119140Snilay@cs.wisc.edu above should be used for selecting the checkpoint, and then figures out 1129140Snilay@cs.wisc.edu the appropriate directory. 1139140Snilay@cs.wisc.edu 1149140Snilay@cs.wisc.edu It also sets the value of the maximum tick value till which the simulation 1159140Snilay@cs.wisc.edu will run. 1169140Snilay@cs.wisc.edu """ 1179140Snilay@cs.wisc.edu 1189140Snilay@cs.wisc.edu from os.path import isdir, exists 1199140Snilay@cs.wisc.edu from os import listdir 1209140Snilay@cs.wisc.edu import re 1219140Snilay@cs.wisc.edu 1229140Snilay@cs.wisc.edu if not isdir(cptdir): 1239140Snilay@cs.wisc.edu fatal("checkpoint dir %s does not exist!", cptdir) 1249140Snilay@cs.wisc.edu 1259140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1269140Snilay@cs.wisc.edu inst = options.checkpoint_restore 1279140Snilay@cs.wisc.edu if options.simpoint: 1289140Snilay@cs.wisc.edu # assume workload 0 has the simpoint 1299140Snilay@cs.wisc.edu if testsys.cpu[0].workload[0].simpoint == 0: 1309140Snilay@cs.wisc.edu fatal('Unable to find simpoint') 1319140Snilay@cs.wisc.edu inst += int(testsys.cpu[0].workload[0].simpoint) 1329140Snilay@cs.wisc.edu 1339140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) 1349140Snilay@cs.wisc.edu if not exists(checkpoint_dir): 1359140Snilay@cs.wisc.edu fatal("Unable to find checkpoint directory %s", checkpoint_dir) 1369140Snilay@cs.wisc.edu else: 1379140Snilay@cs.wisc.edu dirs = listdir(cptdir) 1389140Snilay@cs.wisc.edu expr = re.compile('cpt\.([0-9]*)') 1399140Snilay@cs.wisc.edu cpts = [] 1409140Snilay@cs.wisc.edu for dir in dirs: 1419140Snilay@cs.wisc.edu match = expr.match(dir) 1429140Snilay@cs.wisc.edu if match: 1439140Snilay@cs.wisc.edu cpts.append(match.group(1)) 1449140Snilay@cs.wisc.edu 1459140Snilay@cs.wisc.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 1469140Snilay@cs.wisc.edu 1479140Snilay@cs.wisc.edu cpt_num = options.checkpoint_restore 1489140Snilay@cs.wisc.edu if cpt_num > len(cpts): 1499140Snilay@cs.wisc.edu fatal('Checkpoint %d not found', cpt_num) 1509140Snilay@cs.wisc.edu 1519140Snilay@cs.wisc.edu maxtick = maxtick - int(cpts[cpt_num - 1]) 1529140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 1539140Snilay@cs.wisc.edu 1549140Snilay@cs.wisc.edu return maxtick, checkpoint_dir 1559140Snilay@cs.wisc.edu 1569215Sandreas.hansson@arm.comdef scriptCheckpoints(options, maxtick, cptdir): 1579140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1589140Snilay@cs.wisc.edu checkpoint_inst = int(options.take_checkpoints) 1599140Snilay@cs.wisc.edu 1609140Snilay@cs.wisc.edu # maintain correct offset if we restored from some instruction 1619140Snilay@cs.wisc.edu if options.checkpoint_restore != None: 1629140Snilay@cs.wisc.edu checkpoint_inst += options.checkpoint_restore 1639140Snilay@cs.wisc.edu 1649140Snilay@cs.wisc.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 1659140Snilay@cs.wisc.edu exit_event = m5.simulate() 1669140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1679140Snilay@cs.wisc.edu print "exit cause = %s" % exit_cause 1689140Snilay@cs.wisc.edu 1699140Snilay@cs.wisc.edu # skip checkpoint instructions should they exist 1709140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 1719140Snilay@cs.wisc.edu exit_event = m5.simulate() 1729140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1739140Snilay@cs.wisc.edu 1749140Snilay@cs.wisc.edu if exit_cause == "a thread reached the max instruction count": 1759140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 1769140Snilay@cs.wisc.edu (options.bench, checkpoint_inst))) 1779140Snilay@cs.wisc.edu print "Checkpoint written." 1789140Snilay@cs.wisc.edu 1799140Snilay@cs.wisc.edu else: 1809140Snilay@cs.wisc.edu when, period = options.take_checkpoints.split(",", 1) 1819140Snilay@cs.wisc.edu when = int(when) 1829140Snilay@cs.wisc.edu period = int(period) 1839156Sandreas.hansson@arm.com num_checkpoints = 0 1849140Snilay@cs.wisc.edu 1859140Snilay@cs.wisc.edu exit_event = m5.simulate(when) 1869140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1879140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 1889140Snilay@cs.wisc.edu exit_event = m5.simulate(when - m5.curTick()) 1899140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1909140Snilay@cs.wisc.edu 1919140Snilay@cs.wisc.edu if exit_cause == "simulate() limit reached": 1929140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 1939140Snilay@cs.wisc.edu num_checkpoints += 1 1949140Snilay@cs.wisc.edu 1959140Snilay@cs.wisc.edu sim_ticks = when 1969140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 1979140Snilay@cs.wisc.edu 1989140Snilay@cs.wisc.edu while num_checkpoints < max_checkpoints and \ 1999140Snilay@cs.wisc.edu exit_cause == "simulate() limit reached": 2009140Snilay@cs.wisc.edu if (sim_ticks + period) > maxtick: 2019140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - sim_ticks) 2029140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2039140Snilay@cs.wisc.edu break 2049140Snilay@cs.wisc.edu else: 2059140Snilay@cs.wisc.edu exit_event = m5.simulate(period) 2069140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2079140Snilay@cs.wisc.edu sim_ticks += period 2089140Snilay@cs.wisc.edu while exit_event.getCause() == "checkpoint": 2099140Snilay@cs.wisc.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 2109140Snilay@cs.wisc.edu if exit_event.getCause() == "simulate() limit reached": 2119140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2129140Snilay@cs.wisc.edu num_checkpoints += 1 2139140Snilay@cs.wisc.edu 2149140Snilay@cs.wisc.edu return exit_cause 2159140Snilay@cs.wisc.edu 2169140Snilay@cs.wisc.edudef benchCheckpoints(options, maxtick, cptdir): 2179140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick) 2189140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2199140Snilay@cs.wisc.edu 2209140Snilay@cs.wisc.edu num_checkpoints = 0 2219140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2229140Snilay@cs.wisc.edu 2239140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2249140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2259140Snilay@cs.wisc.edu num_checkpoints += 1 2269140Snilay@cs.wisc.edu if num_checkpoints == max_checkpoints: 2279140Snilay@cs.wisc.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 2289140Snilay@cs.wisc.edu break 2299140Snilay@cs.wisc.edu 2309140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2319140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2329140Snilay@cs.wisc.edu 2339140Snilay@cs.wisc.edu return exit_cause 2349140Snilay@cs.wisc.edu 2359151Satgutier@umich.edudef repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, switch_freq): 2369151Satgutier@umich.edu print "starting switch loop" 2379151Satgutier@umich.edu while True: 2389151Satgutier@umich.edu exit_event = m5.simulate(switch_freq) 2399151Satgutier@umich.edu exit_cause = exit_event.getCause() 2409151Satgutier@umich.edu 2419151Satgutier@umich.edu if exit_cause != "simulate() limit reached": 2429151Satgutier@umich.edu return exit_cause 2439151Satgutier@umich.edu 2449151Satgutier@umich.edu print "draining the system" 2459151Satgutier@umich.edu m5.doDrain(testsys) 2469151Satgutier@umich.edu m5.switchCpus(repeat_switch_cpu_list) 2479151Satgutier@umich.edu m5.resume(testsys) 2489151Satgutier@umich.edu 2499151Satgutier@umich.edu tmp_cpu_list = [] 2509151Satgutier@umich.edu for old_cpu, new_cpu in repeat_switch_cpu_list: 2519151Satgutier@umich.edu tmp_cpu_list.append((new_cpu, old_cpu)) 2529151Satgutier@umich.edu repeat_switch_cpu_list = tmp_cpu_list 2539151Satgutier@umich.edu 2549151Satgutier@umich.edu if (maxtick - m5.curTick()) <= switch_freq: 2559151Satgutier@umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2569151Satgutier@umich.edu return exit_event.getCause() 2579151Satgutier@umich.edu 2583481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 2593395Shsul@eecs.umich.edu if options.maxtick: 2603395Shsul@eecs.umich.edu maxtick = options.maxtick 2613395Shsul@eecs.umich.edu elif options.maxtime: 2624167Sbinkertn@umich.edu simtime = m5.ticks.seconds(simtime) 2633395Shsul@eecs.umich.edu print "simulating for: ", simtime 2643395Shsul@eecs.umich.edu maxtick = simtime 2653395Shsul@eecs.umich.edu else: 2663511Shsul@eecs.umich.edu maxtick = m5.MaxTick 2673395Shsul@eecs.umich.edu 2683395Shsul@eecs.umich.edu if options.checkpoint_dir: 2693395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 2705211Ssaidi@eecs.umich.edu elif m5.options.outdir: 2715211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 2723395Shsul@eecs.umich.edu else: 2733395Shsul@eecs.umich.edu cptdir = getcwd() 2743395Shsul@eecs.umich.edu 2755370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 2766654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 2775370Ssaidi@eecs.umich.edu 2785371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 2796654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 2805370Ssaidi@eecs.umich.edu 2819151Satgutier@umich.edu if options.standard_switch and options.repeat_switch: 2829151Satgutier@umich.edu fatal("Can't specify both --standard-switch and --repeat-switch") 2839151Satgutier@umich.edu 2849151Satgutier@umich.edu if options.repeat_switch and options.take_checkpoints: 2859151Satgutier@umich.edu fatal("Can't specify both --repeat-switch and --take-checkpoints") 2869151Satgutier@umich.edu 2873395Shsul@eecs.umich.edu np = options.num_cpus 2883481Shsul@eecs.umich.edu switch_cpus = None 2893481Shsul@eecs.umich.edu 2908318Sksewell@umich.edu if options.prog_interval: 2916144Sksewell@umich.edu for i in xrange(np): 2928311Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_interval 2936144Sksewell@umich.edu 2946641Sksewell@umich.edu if options.maxinsts: 2956641Sksewell@umich.edu for i in xrange(np): 2966641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 2976641Sksewell@umich.edu 2983481Shsul@eecs.umich.edu if cpu_class: 2999151Satgutier@umich.edu switch_cpus = [cpu_class(defer_registration=True, cpu_id=(i)) 3003481Shsul@eecs.umich.edu for i in xrange(np)] 3013481Shsul@eecs.umich.edu 3023481Shsul@eecs.umich.edu for i in xrange(np): 3035361Srstrong@cs.ucsd.edu if options.fast_forward: 3045369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 3053481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 3068803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 3079129Sandreas.hansson@arm.com switch_cpus[i].clock = testsys.cpu[i].clock 3085369Ssaidi@eecs.umich.edu # simulation period 3098311Sksewell@umich.edu if options.maxinsts: 3108311Sksewell@umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 3118887Sgeoffrey.blake@arm.com # Add checker cpu if selected 3128887Sgeoffrey.blake@arm.com if options.checker: 3138887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 3143481Shsul@eecs.umich.edu 3155311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 3163481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 3173395Shsul@eecs.umich.edu 3189151Satgutier@umich.edu if options.repeat_switch: 3199151Satgutier@umich.edu if options.cpu_type == "arm_detailed": 3209151Satgutier@umich.edu if not options.caches: 3219151Satgutier@umich.edu print "O3 CPU must be used with caches" 3229151Satgutier@umich.edu sys.exit(1) 3239151Satgutier@umich.edu 3249151Satgutier@umich.edu repeat_switch_cpus = [O3_ARM_v7a_3(defer_registration=True, \ 3259151Satgutier@umich.edu cpu_id=(i)) for i in xrange(np)] 3269151Satgutier@umich.edu elif options.cpu_type == "detailed": 3279151Satgutier@umich.edu if not options.caches: 3289151Satgutier@umich.edu print "O3 CPU must be used with caches" 3299151Satgutier@umich.edu sys.exit(1) 3309151Satgutier@umich.edu 3319151Satgutier@umich.edu repeat_switch_cpus = [DerivO3CPU(defer_registration=True, \ 3329151Satgutier@umich.edu cpu_id=(i)) for i in xrange(np)] 3339151Satgutier@umich.edu elif options.cpu_type == "inorder": 3349151Satgutier@umich.edu print "inorder CPU switching not supported" 3359151Satgutier@umich.edu sys.exit(1) 3369151Satgutier@umich.edu elif options.cpu_type == "timing": 3379151Satgutier@umich.edu repeat_switch_cpus = [TimingSimpleCPU(defer_registration=True, \ 3389151Satgutier@umich.edu cpu_id=(i)) for i in xrange(np)] 3399151Satgutier@umich.edu else: 3409151Satgutier@umich.edu repeat_switch_cpus = [AtomicSimpleCPU(defer_registration=True, \ 3419151Satgutier@umich.edu cpu_id=(i)) for i in xrange(np)] 3429151Satgutier@umich.edu 3439151Satgutier@umich.edu for i in xrange(np): 3449151Satgutier@umich.edu repeat_switch_cpus[i].system = testsys 3459151Satgutier@umich.edu repeat_switch_cpus[i].workload = testsys.cpu[i].workload 3469151Satgutier@umich.edu repeat_switch_cpus[i].clock = testsys.cpu[i].clock 3479151Satgutier@umich.edu 3489151Satgutier@umich.edu if options.maxinsts: 3499151Satgutier@umich.edu repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts 3509151Satgutier@umich.edu 3519151Satgutier@umich.edu if options.checker: 3529151Satgutier@umich.edu repeat_switch_cpus[i].addCheckerCpu() 3539151Satgutier@umich.edu 3549151Satgutier@umich.edu testsys.repeat_switch_cpus = repeat_switch_cpus 3559151Satgutier@umich.edu 3569151Satgutier@umich.edu if cpu_class: 3579151Satgutier@umich.edu repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) 3589151Satgutier@umich.edu for i in xrange(np)] 3599151Satgutier@umich.edu else: 3609151Satgutier@umich.edu repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) 3619151Satgutier@umich.edu for i in xrange(np)] 3629151Satgutier@umich.edu 3633395Shsul@eecs.umich.edu if options.standard_switch: 3649151Satgutier@umich.edu switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(i)) 3653395Shsul@eecs.umich.edu for i in xrange(np)] 3669151Satgutier@umich.edu switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(i)) 3673395Shsul@eecs.umich.edu for i in xrange(np)] 3683478Shsul@eecs.umich.edu 3693395Shsul@eecs.umich.edu for i in xrange(np): 3703395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 3713478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 3728803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 3738803Sgblack@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 3749129Sandreas.hansson@arm.com switch_cpus[i].clock = testsys.cpu[i].clock 3759129Sandreas.hansson@arm.com switch_cpus_1[i].clock = testsys.cpu[i].clock 3763480Shsul@eecs.umich.edu 3775361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 3785369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 3795361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 3805361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 3815361Srstrong@cs.ucsd.edu elif options.fast_forward: 3825369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 3835361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 3845361Srstrong@cs.ucsd.edu elif options.simpoint: 3855378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 3866654Snate@binkert.org fatal('simpoint not found') 3875361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 3885361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 3895361Srstrong@cs.ucsd.edu # No distance specified, just switch 3905361Srstrong@cs.ucsd.edu else: 3915361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 3925361Srstrong@cs.ucsd.edu 3935361Srstrong@cs.ucsd.edu # warmup period 3945361Srstrong@cs.ucsd.edu if options.warmup_insts: 3955361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 3965361Srstrong@cs.ucsd.edu 3975361Srstrong@cs.ucsd.edu # simulation period 3988311Sksewell@umich.edu if options.maxinsts: 3998311Sksewell@umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 4005353Svilas.sridharan@gmail.com 4018887Sgeoffrey.blake@arm.com # attach the checker cpu if selected 4028887Sgeoffrey.blake@arm.com if options.checker: 4038887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 4048887Sgeoffrey.blake@arm.com switch_cpus_1[i].addCheckerCpu() 4058887Sgeoffrey.blake@arm.com 4068211Satgutier@umich.edu testsys.switch_cpus = switch_cpus 4078211Satgutier@umich.edu testsys.switch_cpus_1 = switch_cpus_1 4088211Satgutier@umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 4098211Satgutier@umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 4103395Shsul@eecs.umich.edu 4115361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 4125369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 4135361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 4145361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 4155361Srstrong@cs.ucsd.edu # Set an instruction break point 4165361Srstrong@cs.ucsd.edu if options.simpoint: 4175361Srstrong@cs.ucsd.edu for i in xrange(np): 4185378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 4196654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 4205369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 4215361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 4225361Srstrong@cs.ucsd.edu # used for output below 4235361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 4245361Srstrong@cs.ucsd.edu else: 4255361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 4265361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 4275361Srstrong@cs.ucsd.edu # for the upcoming simulation 4285361Srstrong@cs.ucsd.edu for i in xrange(np): 4295361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 4305361Srstrong@cs.ucsd.edu 4317531Ssteve.reinhardt@amd.com checkpoint_dir = None 4325369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 4339140Snilay@cs.wisc.edu maxtick, checkpoint_dir = findCptDir(options, maxtick, cptdir, testsys) 4347531Ssteve.reinhardt@amd.com m5.instantiate(checkpoint_dir) 4353395Shsul@eecs.umich.edu 4363481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 4375361Srstrong@cs.ucsd.edu if options.standard_switch: 4385361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 4395361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 4405361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4415361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 4425361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 4435361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 4445361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4455361Srstrong@cs.ucsd.edu else: 4465361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 4475361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 4487766Sgblack@eecs.umich.edu print "Switched CPUS @ tick %s" % (m5.curTick()) 4493395Shsul@eecs.umich.edu 4505361Srstrong@cs.ucsd.edu # when you change to Timing (or Atomic), you halt the system 4515361Srstrong@cs.ucsd.edu # given as argument. When you are finished with the system 4525361Srstrong@cs.ucsd.edu # changes (including switchCpus), you must resume the system 4535361Srstrong@cs.ucsd.edu # manually. You DON'T need to resume after just switching 4545361Srstrong@cs.ucsd.edu # CPUs if you haven't changed anything on the system level. 4553395Shsul@eecs.umich.edu 4563395Shsul@eecs.umich.edu m5.changeToTiming(testsys) 4573395Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list) 4583395Shsul@eecs.umich.edu m5.resume(testsys) 4593395Shsul@eecs.umich.edu 4603481Shsul@eecs.umich.edu if options.standard_switch: 4615361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 4625361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 4635361Srstrong@cs.ucsd.edu 4645361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 4655361Srstrong@cs.ucsd.edu if options.warmup_insts: 4665361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4675361Srstrong@cs.ucsd.edu else: 4689151Satgutier@umich.edu exit_event = m5.simulate(options.standard_switch) 4697766Sgblack@eecs.umich.edu print "Switching CPUS @ tick %s" % (m5.curTick()) 4705361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 4715361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 4725072Ssaidi@eecs.umich.edu m5.drain(testsys) 4733481Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list1) 4745072Ssaidi@eecs.umich.edu m5.resume(testsys) 4753395Shsul@eecs.umich.edu 4767489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 4777489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 4787489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 4797489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 4807489Ssteve.reinhardt@amd.com if options.take_checkpoints and options.checkpoint_restore: 4817489Ssteve.reinhardt@amd.com if m5.options.outdir: 4827489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 4837489Ssteve.reinhardt@amd.com else: 4847489Ssteve.reinhardt@amd.com cptdir = getcwd() 4857489Ssteve.reinhardt@amd.com 4865369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 4879140Snilay@cs.wisc.edu # Checkpoints being taken via the command line at <when> and at 4889140Snilay@cs.wisc.edu # subsequent periods of <period>. Checkpoint instructions 4899140Snilay@cs.wisc.edu # received from the benchmark running are ignored and skipped in 4909140Snilay@cs.wisc.edu # favor of command line checkpoint instructions. 4919215Sandreas.hansson@arm.com exit_cause = scriptCheckpoints(options, maxtick, cptdir) 4929140Snilay@cs.wisc.edu else: 4939151Satgutier@umich.edu if options.fast_forward: 4949151Satgutier@umich.edu m5.stats.reset() 4959151Satgutier@umich.edu print "**** REAL SIMULATION ****" 4969151Satgutier@umich.edu 4979140Snilay@cs.wisc.edu # If checkpoints are being taken, then the checkpoint instruction 4989140Snilay@cs.wisc.edu # will occur in the benchmark code it self. 4999151Satgutier@umich.edu if options.repeat_switch and maxtick > options.repeat_switch: 5009151Satgutier@umich.edu exit_cause = repeatSwitch(testsys, repeat_switch_cpu_list, 5019151Satgutier@umich.edu maxtick, options.repeat_switch) 5029151Satgutier@umich.edu else: 5039151Satgutier@umich.edu exit_cause = benchCheckpoints(options, maxtick, cptdir) 5043395Shsul@eecs.umich.edu 5057766Sgblack@eecs.umich.edu print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 5066776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 5077525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 508