Simulation.py revision 9139
15661Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 25661Sgblack@eecs.umich.edu# Copyright (c) 2010 Advanced Micro Devices, Inc. 35661Sgblack@eecs.umich.edu# All rights reserved. 47087Snate@binkert.org# 57087Snate@binkert.org# Redistribution and use in source and binary forms, with or without 67087Snate@binkert.org# modification, are permitted provided that the following conditions are 77087Snate@binkert.org# met: redistributions of source code must retain the above copyright 87087Snate@binkert.org# notice, this list of conditions and the following disclaimer; 97087Snate@binkert.org# redistributions in binary form must reproduce the above copyright 107087Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 117087Snate@binkert.org# documentation and/or other materials provided with the distribution; 125661Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 137087Snate@binkert.org# contributors may be used to endorse or promote products derived from 147087Snate@binkert.org# this software without specific prior written permission. 157087Snate@binkert.org# 167087Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177087Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187087Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197087Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207087Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215661Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227087Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235661Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245661Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255661Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265661Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275661Sgblack@eecs.umich.edu# 285661Sgblack@eecs.umich.edu# Authors: Lisa Hsu 295661Sgblack@eecs.umich.edu 305661Sgblack@eecs.umich.edufrom os import getcwd 315661Sgblack@eecs.umich.edufrom os.path import join as joinpath 325661Sgblack@eecs.umich.edu 335661Sgblack@eecs.umich.eduimport m5 345661Sgblack@eecs.umich.edufrom m5.defines import buildEnv 355661Sgblack@eecs.umich.edufrom m5.objects import * 365661Sgblack@eecs.umich.edufrom m5.util import * 375661Sgblack@eecs.umich.edufrom O3_ARM_v7a import * 385661Sgblack@eecs.umich.edu 395661Sgblack@eecs.umich.eduaddToPath('../common') 405661Sgblack@eecs.umich.edu 415661Sgblack@eecs.umich.edudef getCPUClass(cpu_type): 425661Sgblack@eecs.umich.edu """Returns the required cpu class and the mode of operation. 435661Sgblack@eecs.umich.edu """ 445661Sgblack@eecs.umich.edu 455661Sgblack@eecs.umich.edu if cpu_type == "timing": 465661Sgblack@eecs.umich.edu return TimingSimpleCPU, 'timing' 475661Sgblack@eecs.umich.edu elif cpu_type == "detailed": 485661Sgblack@eecs.umich.edu return DerivO3CPU, 'timing' 495661Sgblack@eecs.umich.edu elif cpu_type == "arm_detailed": 505661Sgblack@eecs.umich.edu return O3_ARM_v7a_3, 'timing' 515661Sgblack@eecs.umich.edu elif cpu_type == "inorder": 525661Sgblack@eecs.umich.edu return InOrderCPU, 'timing' 535661Sgblack@eecs.umich.edu else: 545661Sgblack@eecs.umich.edu return AtomicSimpleCPU, 'atomic' 555661Sgblack@eecs.umich.edu 565661Sgblack@eecs.umich.edudef setCPUClass(options): 575661Sgblack@eecs.umich.edu """Returns two cpu classes and the initial mode of operation. 585661Sgblack@eecs.umich.edu 595661Sgblack@eecs.umich.edu Restoring from a checkpoint or fast forwarding through a benchmark 605661Sgblack@eecs.umich.edu can be done using one type of cpu, and then the actual 615661Sgblack@eecs.umich.edu simulation can be carried out using another type. This function 625661Sgblack@eecs.umich.edu returns these two types of cpus and the initial mode of operation 635661Sgblack@eecs.umich.edu depending on the options provided. 645661Sgblack@eecs.umich.edu """ 655661Sgblack@eecs.umich.edu 665661Sgblack@eecs.umich.edu if options.cpu_type == "detailed" or \ 675661Sgblack@eecs.umich.edu options.cpu_type == "arm_detailed" or \ 685661Sgblack@eecs.umich.edu options.cpu_type == "inorder" : 695661Sgblack@eecs.umich.edu if not options.caches and not options.ruby: 705661Sgblack@eecs.umich.edu fatal("O3/Inorder CPU must be used with caches") 715661Sgblack@eecs.umich.edu 725661Sgblack@eecs.umich.edu TmpClass, test_mem_mode = getCPUClass(options.cpu_type) 735661Sgblack@eecs.umich.edu CPUClass = None 745661Sgblack@eecs.umich.edu 755661Sgblack@eecs.umich.edu if options.checkpoint_restore != None: 765661Sgblack@eecs.umich.edu if options.restore_with_cpu != options.cpu_type: 775661Sgblack@eecs.umich.edu CPUClass = TmpClass 785661Sgblack@eecs.umich.edu TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu) 795661Sgblack@eecs.umich.edu elif options.fast_forward: 805661Sgblack@eecs.umich.edu CPUClass = TmpClass 815661Sgblack@eecs.umich.edu TmpClass = AtomicSimpleCPU 825661Sgblack@eecs.umich.edu test_mem_mode = 'atomic' 835661Sgblack@eecs.umich.edu 845661Sgblack@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 855661Sgblack@eecs.umich.edu 865661Sgblack@eecs.umich.edudef setWorkCountOptions(system, options): 875661Sgblack@eecs.umich.edu if options.work_item_id != None: 885661Sgblack@eecs.umich.edu system.work_item_id = options.work_item_id 895661Sgblack@eecs.umich.edu if options.work_begin_cpu_id_exit != None: 905661Sgblack@eecs.umich.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 915661Sgblack@eecs.umich.edu if options.work_end_exit_count != None: 925661Sgblack@eecs.umich.edu system.work_end_exit_count = options.work_end_exit_count 935661Sgblack@eecs.umich.edu if options.work_end_checkpoint_count != None: 945661Sgblack@eecs.umich.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 955661Sgblack@eecs.umich.edu if options.work_begin_exit_count != None: 965661Sgblack@eecs.umich.edu system.work_begin_exit_count = options.work_begin_exit_count 975661Sgblack@eecs.umich.edu if options.work_begin_checkpoint_count != None: 985661Sgblack@eecs.umich.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 995661Sgblack@eecs.umich.edu if options.work_cpus_checkpoint_count != None: 1005661Sgblack@eecs.umich.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 1015661Sgblack@eecs.umich.edu 1025661Sgblack@eecs.umich.edudef run(options, root, testsys, cpu_class): 1035661Sgblack@eecs.umich.edu if options.maxtick: 1045661Sgblack@eecs.umich.edu maxtick = options.maxtick 1055661Sgblack@eecs.umich.edu elif options.maxtime: 1065661Sgblack@eecs.umich.edu simtime = m5.ticks.seconds(simtime) 1075661Sgblack@eecs.umich.edu print "simulating for: ", simtime 1085661Sgblack@eecs.umich.edu maxtick = simtime 1095661Sgblack@eecs.umich.edu else: 1105661Sgblack@eecs.umich.edu maxtick = m5.MaxTick 1115661Sgblack@eecs.umich.edu 1125661Sgblack@eecs.umich.edu if options.checkpoint_dir: 1135661Sgblack@eecs.umich.edu cptdir = options.checkpoint_dir 1145661Sgblack@eecs.umich.edu elif m5.options.outdir: 1155661Sgblack@eecs.umich.edu cptdir = m5.options.outdir 1165661Sgblack@eecs.umich.edu else: 1175661Sgblack@eecs.umich.edu cptdir = getcwd() 1185661Sgblack@eecs.umich.edu 1195661Sgblack@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 1205661Sgblack@eecs.umich.edu fatal("Can't specify both --fast-forward and --checkpoint-restore") 1215661Sgblack@eecs.umich.edu 1225661Sgblack@eecs.umich.edu if options.standard_switch and not options.caches: 1235661Sgblack@eecs.umich.edu fatal("Must specify --caches when using --standard-switch") 1245661Sgblack@eecs.umich.edu 1255661Sgblack@eecs.umich.edu np = options.num_cpus 1265661Sgblack@eecs.umich.edu max_checkpoints = options.max_checkpoints 1275661Sgblack@eecs.umich.edu switch_cpus = None 1285661Sgblack@eecs.umich.edu 1295661Sgblack@eecs.umich.edu if options.prog_interval: 1305661Sgblack@eecs.umich.edu for i in xrange(np): 1315661Sgblack@eecs.umich.edu testsys.cpu[i].progress_interval = options.prog_interval 1325661Sgblack@eecs.umich.edu 1335661Sgblack@eecs.umich.edu if options.maxinsts: 1345661Sgblack@eecs.umich.edu for i in xrange(np): 1355661Sgblack@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 1365661Sgblack@eecs.umich.edu 1375661Sgblack@eecs.umich.edu if cpu_class: 1385661Sgblack@eecs.umich.edu switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 1395661Sgblack@eecs.umich.edu for i in xrange(np)] 1405661Sgblack@eecs.umich.edu 1415661Sgblack@eecs.umich.edu for i in xrange(np): 1425661Sgblack@eecs.umich.edu if options.fast_forward: 1435661Sgblack@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1445661Sgblack@eecs.umich.edu switch_cpus[i].system = testsys 1455661Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1465661Sgblack@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[i].clock 1475661Sgblack@eecs.umich.edu # simulation period 1485661Sgblack@eecs.umich.edu if options.maxinsts: 1495661Sgblack@eecs.umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 1505661Sgblack@eecs.umich.edu # Add checker cpu if selected 1515661Sgblack@eecs.umich.edu if options.checker: 1525661Sgblack@eecs.umich.edu switch_cpus[i].addCheckerCpu() 1535661Sgblack@eecs.umich.edu 1545662Sgblack@eecs.umich.edu testsys.switch_cpus = switch_cpus 1555661Sgblack@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1565661Sgblack@eecs.umich.edu 1575661Sgblack@eecs.umich.edu if options.standard_switch: 1585661Sgblack@eecs.umich.edu if not options.caches: 1595661Sgblack@eecs.umich.edu # O3 CPU must have a cache to work. 1605661Sgblack@eecs.umich.edu print "O3 CPU must be used with caches" 1615661Sgblack@eecs.umich.edu sys.exit(1) 1625661Sgblack@eecs.umich.edu 1635661Sgblack@eecs.umich.edu switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 1645661Sgblack@eecs.umich.edu for i in xrange(np)] 1655661Sgblack@eecs.umich.edu switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 1665788Sgblack@eecs.umich.edu for i in xrange(np)] 1675661Sgblack@eecs.umich.edu 1685661Sgblack@eecs.umich.edu for i in xrange(np): 1695661Sgblack@eecs.umich.edu switch_cpus[i].system = testsys 1705661Sgblack@eecs.umich.edu switch_cpus_1[i].system = testsys 1715661Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1725661Sgblack@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 1735661Sgblack@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[i].clock 1745662Sgblack@eecs.umich.edu switch_cpus_1[i].clock = testsys.cpu[i].clock 1755662Sgblack@eecs.umich.edu 1765662Sgblack@eecs.umich.edu # if restoring, make atomic cpu simulate only a few instructions 1775662Sgblack@eecs.umich.edu if options.checkpoint_restore != None: 1785662Sgblack@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = 1 1795662Sgblack@eecs.umich.edu # Fast forward to specified location if we are not restoring 1805692Sgblack@eecs.umich.edu elif options.fast_forward: 1815662Sgblack@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1825662Sgblack@eecs.umich.edu # Fast forward to a simpoint (warning: time consuming) 1835662Sgblack@eecs.umich.edu elif options.simpoint: 1845663Sgblack@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 1855663Sgblack@eecs.umich.edu fatal('simpoint not found') 1865663Sgblack@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = \ 1875663Sgblack@eecs.umich.edu testsys.cpu[i].workload[0].simpoint 1885663Sgblack@eecs.umich.edu # No distance specified, just switch 1895663Sgblack@eecs.umich.edu else: 1905663Sgblack@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = 1 1915663Sgblack@eecs.umich.edu 1925663Sgblack@eecs.umich.edu # warmup period 1935663Sgblack@eecs.umich.edu if options.warmup_insts: 1945663Sgblack@eecs.umich.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 1955663Sgblack@eecs.umich.edu 1965663Sgblack@eecs.umich.edu # simulation period 1975663Sgblack@eecs.umich.edu if options.maxinsts: 1985663Sgblack@eecs.umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 1995663Sgblack@eecs.umich.edu 2005692Sgblack@eecs.umich.edu # attach the checker cpu if selected 2015663Sgblack@eecs.umich.edu if options.checker: 2025663Sgblack@eecs.umich.edu switch_cpus[i].addCheckerCpu() 2035663Sgblack@eecs.umich.edu switch_cpus_1[i].addCheckerCpu() 2045661Sgblack@eecs.umich.edu 2055661Sgblack@eecs.umich.edu testsys.switch_cpus = switch_cpus 2065661Sgblack@eecs.umich.edu testsys.switch_cpus_1 = switch_cpus_1 2075661Sgblack@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 2085661Sgblack@eecs.umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 2095661Sgblack@eecs.umich.edu 2105661Sgblack@eecs.umich.edu # set the checkpoint in the cpu before m5.instantiate is called 2115661Sgblack@eecs.umich.edu if options.take_checkpoints != None and \ 2125661Sgblack@eecs.umich.edu (options.simpoint or options.at_instruction): 2135661Sgblack@eecs.umich.edu offset = int(options.take_checkpoints) 2145661Sgblack@eecs.umich.edu # Set an instruction break point 2155661Sgblack@eecs.umich.edu if options.simpoint: 2165661Sgblack@eecs.umich.edu for i in xrange(np): 2175661Sgblack@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 2185661Sgblack@eecs.umich.edu fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 2195663Sgblack@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 2205663Sgblack@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 2215663Sgblack@eecs.umich.edu # used for output below 2225663Sgblack@eecs.umich.edu options.take_checkpoints = checkpoint_inst 2235663Sgblack@eecs.umich.edu else: 2245663Sgblack@eecs.umich.edu options.take_checkpoints = offset 2255663Sgblack@eecs.umich.edu # Set all test cpus with the right number of instructions 2265663Sgblack@eecs.umich.edu # for the upcoming simulation 2275663Sgblack@eecs.umich.edu for i in xrange(np): 2285663Sgblack@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = offset 2295663Sgblack@eecs.umich.edu 2305663Sgblack@eecs.umich.edu checkpoint_dir = None 2315663Sgblack@eecs.umich.edu if options.checkpoint_restore != None: 2325663Sgblack@eecs.umich.edu from os.path import isdir, exists 2335661Sgblack@eecs.umich.edu from os import listdir 234 import re 235 236 if not isdir(cptdir): 237 fatal("checkpoint dir %s does not exist!", cptdir) 238 239 if options.at_instruction or options.simpoint: 240 inst = options.checkpoint_restore 241 if options.simpoint: 242 # assume workload 0 has the simpoint 243 if testsys.cpu[0].workload[0].simpoint == 0: 244 fatal('Unable to find simpoint') 245 inst += int(testsys.cpu[0].workload[0].simpoint) 246 247 checkpoint_dir = joinpath(cptdir, 248 "cpt.%s.%s" % (options.bench, inst)) 249 if not exists(checkpoint_dir): 250 fatal("Unable to find checkpoint directory %s", checkpoint_dir) 251 else: 252 dirs = listdir(cptdir) 253 expr = re.compile('cpt\.([0-9]*)') 254 cpts = [] 255 for dir in dirs: 256 match = expr.match(dir) 257 if match: 258 cpts.append(match.group(1)) 259 260 cpts.sort(lambda a,b: cmp(long(a), long(b))) 261 262 cpt_num = options.checkpoint_restore 263 264 if cpt_num > len(cpts): 265 fatal('Checkpoint %d not found', cpt_num) 266 267 ## Adjust max tick based on our starting tick 268 maxtick = maxtick - int(cpts[cpt_num - 1]) 269 checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 270 271 m5.instantiate(checkpoint_dir) 272 273 if options.standard_switch or cpu_class: 274 if options.standard_switch: 275 print "Switch at instruction count:%s" % \ 276 str(testsys.cpu[0].max_insts_any_thread) 277 exit_event = m5.simulate() 278 elif cpu_class and options.fast_forward: 279 print "Switch at instruction count:%s" % \ 280 str(testsys.cpu[0].max_insts_any_thread) 281 exit_event = m5.simulate() 282 else: 283 print "Switch at curTick count:%s" % str(10000) 284 exit_event = m5.simulate(10000) 285 print "Switched CPUS @ tick %s" % (m5.curTick()) 286 287 # when you change to Timing (or Atomic), you halt the system 288 # given as argument. When you are finished with the system 289 # changes (including switchCpus), you must resume the system 290 # manually. You DON'T need to resume after just switching 291 # CPUs if you haven't changed anything on the system level. 292 293 m5.changeToTiming(testsys) 294 m5.switchCpus(switch_cpu_list) 295 m5.resume(testsys) 296 297 if options.standard_switch: 298 print "Switch at instruction count:%d" % \ 299 (testsys.switch_cpus[0].max_insts_any_thread) 300 301 #warmup instruction count may have already been set 302 if options.warmup_insts: 303 exit_event = m5.simulate() 304 else: 305 exit_event = m5.simulate(options.warmup) 306 print "Switching CPUS @ tick %s" % (m5.curTick()) 307 print "Simulation ends instruction count:%d" % \ 308 (testsys.switch_cpus_1[0].max_insts_any_thread) 309 m5.drain(testsys) 310 m5.switchCpus(switch_cpu_list1) 311 m5.resume(testsys) 312 313 num_checkpoints = 0 314 exit_cause = '' 315 316 # If we're taking and restoring checkpoints, use checkpoint_dir 317 # option only for finding the checkpoints to restore from. This 318 # lets us test checkpointing by restoring from one set of 319 # checkpoints, generating a second set, and then comparing them. 320 if options.take_checkpoints and options.checkpoint_restore: 321 if m5.options.outdir: 322 cptdir = m5.options.outdir 323 else: 324 cptdir = getcwd() 325 326 # Checkpoints being taken via the command line at <when> and at 327 # subsequent periods of <period>. Checkpoint instructions 328 # received from the benchmark running are ignored and skipped in 329 # favor of command line checkpoint instructions. 330 if options.take_checkpoints != None : 331 if options.at_instruction or options.simpoint: 332 checkpoint_inst = int(options.take_checkpoints) 333 334 # maintain correct offset if we restored from some instruction 335 if options.checkpoint_restore != None: 336 checkpoint_inst += options.checkpoint_restore 337 338 print "Creating checkpoint at inst:%d" % (checkpoint_inst) 339 exit_event = m5.simulate() 340 print "exit cause = %s" % (exit_event.getCause()) 341 342 # skip checkpoint instructions should they exist 343 while exit_event.getCause() == "checkpoint": 344 exit_event = m5.simulate() 345 346 if exit_event.getCause() == \ 347 "a thread reached the max instruction count": 348 m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 349 (options.bench, checkpoint_inst))) 350 print "Checkpoint written." 351 num_checkpoints += 1 352 353 if exit_event.getCause() == "user interrupt received": 354 exit_cause = exit_event.getCause(); 355 else: 356 when, period = options.take_checkpoints.split(",", 1) 357 when = int(when) 358 period = int(period) 359 360 exit_event = m5.simulate(when) 361 while exit_event.getCause() == "checkpoint": 362 exit_event = m5.simulate(when - m5.curTick()) 363 364 if exit_event.getCause() == "simulate() limit reached": 365 m5.checkpoint(joinpath(cptdir, "cpt.%d")) 366 num_checkpoints += 1 367 368 sim_ticks = when 369 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 370 while num_checkpoints < max_checkpoints and \ 371 exit_event.getCause() == "simulate() limit reached": 372 if (sim_ticks + period) > maxtick: 373 exit_event = m5.simulate(maxtick - sim_ticks) 374 exit_cause = exit_event.getCause() 375 break 376 else: 377 exit_event = m5.simulate(period) 378 sim_ticks += period 379 while exit_event.getCause() == "checkpoint": 380 exit_event = m5.simulate(sim_ticks - m5.curTick()) 381 if exit_event.getCause() == "simulate() limit reached": 382 m5.checkpoint(joinpath(cptdir, "cpt.%d")) 383 num_checkpoints += 1 384 385 if exit_event.getCause() != "simulate() limit reached": 386 exit_cause = exit_event.getCause(); 387 388 else: # no checkpoints being taken via this script 389 if options.fast_forward: 390 m5.stats.reset() 391 print "**** REAL SIMULATION ****" 392 exit_event = m5.simulate(maxtick) 393 394 while exit_event.getCause() == "checkpoint": 395 m5.checkpoint(joinpath(cptdir, "cpt.%d")) 396 num_checkpoints += 1 397 if num_checkpoints == max_checkpoints: 398 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 399 break 400 401 exit_event = m5.simulate(maxtick - m5.curTick()) 402 exit_cause = exit_event.getCause() 403 404 if exit_cause == '': 405 exit_cause = exit_event.getCause() 406 print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 407 408 if options.checkpoint_at_end: 409 m5.checkpoint(joinpath(cptdir, "cpt.%d")) 410 411