Simulation.py revision 8318
15347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 27534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 33395Shsul@eecs.umich.edu# All rights reserved. 43395Shsul@eecs.umich.edu# 53395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 63395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 73395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 83395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 93395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 103395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 113395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 123395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 133395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143395Shsul@eecs.umich.edu# this software without specific prior written permission. 153395Shsul@eecs.umich.edu# 163395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# Authors: Lisa Hsu 293395Shsul@eecs.umich.edu 303395Shsul@eecs.umich.edufrom os import getcwd 313509Shsul@eecs.umich.edufrom os.path import join as joinpath 326654Snate@binkert.org 333395Shsul@eecs.umich.eduimport m5 346654Snate@binkert.orgfrom m5.defines import buildEnv 353395Shsul@eecs.umich.edufrom m5.objects import * 366654Snate@binkert.orgfrom m5.util import * 376654Snate@binkert.org 386654Snate@binkert.orgaddToPath('../common') 393395Shsul@eecs.umich.edu 403481Shsul@eecs.umich.edudef setCPUClass(options): 413481Shsul@eecs.umich.edu 423481Shsul@eecs.umich.edu atomic = False 433481Shsul@eecs.umich.edu if options.timing: 445347Ssaidi@eecs.umich.edu class TmpClass(TimingSimpleCPU): pass 453481Shsul@eecs.umich.edu elif options.detailed: 463681Sktlim@umich.edu if not options.caches: 473681Sktlim@umich.edu print "O3 CPU must be used with caches" 483681Sktlim@umich.edu sys.exit(1) 495347Ssaidi@eecs.umich.edu class TmpClass(DerivO3CPU): pass 505869Sksewell@umich.edu elif options.inorder: 515869Sksewell@umich.edu if not options.caches: 525869Sksewell@umich.edu print "InOrder CPU must be used with caches" 535869Sksewell@umich.edu sys.exit(1) 545869Sksewell@umich.edu class TmpClass(InOrderCPU): pass 553481Shsul@eecs.umich.edu else: 565347Ssaidi@eecs.umich.edu class TmpClass(AtomicSimpleCPU): pass 573481Shsul@eecs.umich.edu atomic = True 583481Shsul@eecs.umich.edu 593481Shsul@eecs.umich.edu CPUClass = None 603481Shsul@eecs.umich.edu test_mem_mode = 'atomic' 613481Shsul@eecs.umich.edu 623481Shsul@eecs.umich.edu if not atomic: 635369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None or options.fast_forward: 643481Shsul@eecs.umich.edu CPUClass = TmpClass 655347Ssaidi@eecs.umich.edu class TmpClass(AtomicSimpleCPU): pass 663481Shsul@eecs.umich.edu else: 673481Shsul@eecs.umich.edu test_mem_mode = 'timing' 683481Shsul@eecs.umich.edu 693481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 703481Shsul@eecs.umich.edu 713481Shsul@eecs.umich.edu 723481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 733395Shsul@eecs.umich.edu if options.maxtick: 743395Shsul@eecs.umich.edu maxtick = options.maxtick 753395Shsul@eecs.umich.edu elif options.maxtime: 764167Sbinkertn@umich.edu simtime = m5.ticks.seconds(simtime) 773395Shsul@eecs.umich.edu print "simulating for: ", simtime 783395Shsul@eecs.umich.edu maxtick = simtime 793395Shsul@eecs.umich.edu else: 803511Shsul@eecs.umich.edu maxtick = m5.MaxTick 813395Shsul@eecs.umich.edu 823395Shsul@eecs.umich.edu if options.checkpoint_dir: 833395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 845211Ssaidi@eecs.umich.edu elif m5.options.outdir: 855211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 863395Shsul@eecs.umich.edu else: 873395Shsul@eecs.umich.edu cptdir = getcwd() 883395Shsul@eecs.umich.edu 895370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 906654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 915370Ssaidi@eecs.umich.edu 925371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 936654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 945370Ssaidi@eecs.umich.edu 953395Shsul@eecs.umich.edu np = options.num_cpus 963395Shsul@eecs.umich.edu max_checkpoints = options.max_checkpoints 973481Shsul@eecs.umich.edu switch_cpus = None 983481Shsul@eecs.umich.edu 998318Sksewell@umich.edu if options.prog_interval: 1006144Sksewell@umich.edu for i in xrange(np): 1018311Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_interval 1026144Sksewell@umich.edu 1036641Sksewell@umich.edu if options.maxinsts: 1046641Sksewell@umich.edu for i in xrange(np): 1056641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 1066641Sksewell@umich.edu 1073481Shsul@eecs.umich.edu if cpu_class: 1083481Shsul@eecs.umich.edu switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 1093481Shsul@eecs.umich.edu for i in xrange(np)] 1103481Shsul@eecs.umich.edu 1113481Shsul@eecs.umich.edu for i in xrange(np): 1125361Srstrong@cs.ucsd.edu if options.fast_forward: 1135369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1143481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1156654Snate@binkert.org if not buildEnv['FULL_SYSTEM']: 1163481Shsul@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1173481Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 1185369Ssaidi@eecs.umich.edu # simulation period 1198311Sksewell@umich.edu if options.maxinsts: 1208311Sksewell@umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 1213481Shsul@eecs.umich.edu 1225311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 1233481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1243395Shsul@eecs.umich.edu 1253395Shsul@eecs.umich.edu if options.standard_switch: 1268211Satgutier@umich.edu if not options.caches: 1278211Satgutier@umich.edu # O3 CPU must have a cache to work. 1288211Satgutier@umich.edu print "O3 CPU must be used with caches" 1298211Satgutier@umich.edu sys.exit(1) 1308211Satgutier@umich.edu 1313395Shsul@eecs.umich.edu switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 1323395Shsul@eecs.umich.edu for i in xrange(np)] 1333478Shsul@eecs.umich.edu switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 1343395Shsul@eecs.umich.edu for i in xrange(np)] 1353478Shsul@eecs.umich.edu 1363395Shsul@eecs.umich.edu for i in xrange(np): 1373395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1383478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 1396654Snate@binkert.org if not buildEnv['FULL_SYSTEM']: 1403395Shsul@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1413478Shsul@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 1423395Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 1433478Shsul@eecs.umich.edu switch_cpus_1[i].clock = testsys.cpu[0].clock 1443480Shsul@eecs.umich.edu 1455361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 1465369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 1475361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1485361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 1495361Srstrong@cs.ucsd.edu elif options.fast_forward: 1505369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1515361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 1525361Srstrong@cs.ucsd.edu elif options.simpoint: 1535378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 1546654Snate@binkert.org fatal('simpoint not found') 1555361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 1565361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 1575361Srstrong@cs.ucsd.edu # No distance specified, just switch 1585361Srstrong@cs.ucsd.edu else: 1595361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1605361Srstrong@cs.ucsd.edu 1615361Srstrong@cs.ucsd.edu # warmup period 1625361Srstrong@cs.ucsd.edu if options.warmup_insts: 1635361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 1645361Srstrong@cs.ucsd.edu 1655361Srstrong@cs.ucsd.edu # simulation period 1668311Sksewell@umich.edu if options.maxinsts: 1678311Sksewell@umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 1685353Svilas.sridharan@gmail.com 1698211Satgutier@umich.edu testsys.switch_cpus = switch_cpus 1708211Satgutier@umich.edu testsys.switch_cpus_1 = switch_cpus_1 1718211Satgutier@umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1728211Satgutier@umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 1733395Shsul@eecs.umich.edu 1745361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 1755369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 1765361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 1775361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 1785361Srstrong@cs.ucsd.edu # Set an instruction break point 1795361Srstrong@cs.ucsd.edu if options.simpoint: 1805361Srstrong@cs.ucsd.edu for i in xrange(np): 1815378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 1826654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 1835369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 1845361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 1855361Srstrong@cs.ucsd.edu # used for output below 1865361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 1875361Srstrong@cs.ucsd.edu else: 1885361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 1895361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 1905361Srstrong@cs.ucsd.edu # for the upcoming simulation 1915361Srstrong@cs.ucsd.edu for i in xrange(np): 1925361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 1935361Srstrong@cs.ucsd.edu 1947531Ssteve.reinhardt@amd.com checkpoint_dir = None 1955369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 1965361Srstrong@cs.ucsd.edu from os.path import isdir, exists 1973395Shsul@eecs.umich.edu from os import listdir 1983395Shsul@eecs.umich.edu import re 1993395Shsul@eecs.umich.edu 2003395Shsul@eecs.umich.edu if not isdir(cptdir): 2016654Snate@binkert.org fatal("checkpoint dir %s does not exist!", cptdir) 2023395Shsul@eecs.umich.edu 2037530Ssteve.reinhardt@amd.com if options.at_instruction or options.simpoint: 2047530Ssteve.reinhardt@amd.com inst = options.checkpoint_restore 2057530Ssteve.reinhardt@amd.com if options.simpoint: 2067530Ssteve.reinhardt@amd.com # assume workload 0 has the simpoint 2077530Ssteve.reinhardt@amd.com if testsys.cpu[0].workload[0].simpoint == 0: 2087530Ssteve.reinhardt@amd.com fatal('Unable to find simpoint') 2097530Ssteve.reinhardt@amd.com inst += int(testsys.cpu[0].workload[0].simpoint) 2107530Ssteve.reinhardt@amd.com 2117530Ssteve.reinhardt@amd.com checkpoint_dir = joinpath(cptdir, 2127530Ssteve.reinhardt@amd.com "cpt.%s.%s" % (options.bench, inst)) 2135361Srstrong@cs.ucsd.edu if not exists(checkpoint_dir): 2146654Snate@binkert.org fatal("Unable to find checkpoint directory %s", checkpoint_dir) 2155361Srstrong@cs.ucsd.edu else: 2165361Srstrong@cs.ucsd.edu dirs = listdir(cptdir) 2175361Srstrong@cs.ucsd.edu expr = re.compile('cpt\.([0-9]*)') 2185361Srstrong@cs.ucsd.edu cpts = [] 2195361Srstrong@cs.ucsd.edu for dir in dirs: 2205361Srstrong@cs.ucsd.edu match = expr.match(dir) 2215361Srstrong@cs.ucsd.edu if match: 2225361Srstrong@cs.ucsd.edu cpts.append(match.group(1)) 2233999Ssaidi@eecs.umich.edu 2245361Srstrong@cs.ucsd.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 2255361Srstrong@cs.ucsd.edu 2265361Srstrong@cs.ucsd.edu cpt_num = options.checkpoint_restore 2275361Srstrong@cs.ucsd.edu 2285361Srstrong@cs.ucsd.edu if cpt_num > len(cpts): 2296654Snate@binkert.org fatal('Checkpoint %d not found', cpt_num) 2305361Srstrong@cs.ucsd.edu 2315361Srstrong@cs.ucsd.edu ## Adjust max tick based on our starting tick 2325361Srstrong@cs.ucsd.edu maxtick = maxtick - int(cpts[cpt_num - 1]) 2337531Ssteve.reinhardt@amd.com checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 2345361Srstrong@cs.ucsd.edu 2357531Ssteve.reinhardt@amd.com m5.instantiate(checkpoint_dir) 2363395Shsul@eecs.umich.edu 2373481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 2385361Srstrong@cs.ucsd.edu if options.standard_switch: 2395361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2405361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2415361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2425361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 2435361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2445361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2455361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2465361Srstrong@cs.ucsd.edu else: 2475361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 2485361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 2497766Sgblack@eecs.umich.edu print "Switched CPUS @ tick %s" % (m5.curTick()) 2503395Shsul@eecs.umich.edu 2515361Srstrong@cs.ucsd.edu # when you change to Timing (or Atomic), you halt the system 2525361Srstrong@cs.ucsd.edu # given as argument. When you are finished with the system 2535361Srstrong@cs.ucsd.edu # changes (including switchCpus), you must resume the system 2545361Srstrong@cs.ucsd.edu # manually. You DON'T need to resume after just switching 2555361Srstrong@cs.ucsd.edu # CPUs if you haven't changed anything on the system level. 2563395Shsul@eecs.umich.edu 2573395Shsul@eecs.umich.edu m5.changeToTiming(testsys) 2583395Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list) 2593395Shsul@eecs.umich.edu m5.resume(testsys) 2603395Shsul@eecs.umich.edu 2613481Shsul@eecs.umich.edu if options.standard_switch: 2625361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 2635361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 2645361Srstrong@cs.ucsd.edu 2655361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 2665361Srstrong@cs.ucsd.edu if options.warmup_insts: 2675361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2685361Srstrong@cs.ucsd.edu else: 2695353Svilas.sridharan@gmail.com exit_event = m5.simulate(options.warmup) 2707766Sgblack@eecs.umich.edu print "Switching CPUS @ tick %s" % (m5.curTick()) 2715361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 2725361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 2735072Ssaidi@eecs.umich.edu m5.drain(testsys) 2743481Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list1) 2755072Ssaidi@eecs.umich.edu m5.resume(testsys) 2763395Shsul@eecs.umich.edu 2773395Shsul@eecs.umich.edu num_checkpoints = 0 2783395Shsul@eecs.umich.edu exit_cause = '' 2793395Shsul@eecs.umich.edu 2807489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 2817489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 2827489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 2837489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 2847489Ssteve.reinhardt@amd.com if options.take_checkpoints and options.checkpoint_restore: 2857489Ssteve.reinhardt@amd.com if m5.options.outdir: 2867489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 2877489Ssteve.reinhardt@amd.com else: 2887489Ssteve.reinhardt@amd.com cptdir = getcwd() 2897489Ssteve.reinhardt@amd.com 2905361Srstrong@cs.ucsd.edu # Checkpoints being taken via the command line at <when> and at 2915361Srstrong@cs.ucsd.edu # subsequent periods of <period>. Checkpoint instructions 2925361Srstrong@cs.ucsd.edu # received from the benchmark running are ignored and skipped in 2935361Srstrong@cs.ucsd.edu # favor of command line checkpoint instructions. 2945369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 2955361Srstrong@cs.ucsd.edu if options.at_instruction or options.simpoint: 2965369Ssaidi@eecs.umich.edu checkpoint_inst = int(options.take_checkpoints) 2973395Shsul@eecs.umich.edu 2985361Srstrong@cs.ucsd.edu # maintain correct offset if we restored from some instruction 2995369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 3005361Srstrong@cs.ucsd.edu checkpoint_inst += options.checkpoint_restore 3013395Shsul@eecs.umich.edu 3025361Srstrong@cs.ucsd.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 3035361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3045361Srstrong@cs.ucsd.edu print "exit cause = %s" % (exit_event.getCause()) 3053395Shsul@eecs.umich.edu 3065361Srstrong@cs.ucsd.edu # skip checkpoint instructions should they exist 3075361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3085361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3093999Ssaidi@eecs.umich.edu 3105361Srstrong@cs.ucsd.edu if exit_event.getCause() == \ 3115361Srstrong@cs.ucsd.edu "a thread reached the max instruction count": 3127525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 3135361Srstrong@cs.ucsd.edu (options.bench, checkpoint_inst))) 3145361Srstrong@cs.ucsd.edu print "Checkpoint written." 3155361Srstrong@cs.ucsd.edu num_checkpoints += 1 3163999Ssaidi@eecs.umich.edu 3175361Srstrong@cs.ucsd.edu if exit_event.getCause() == "user interrupt received": 3185361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3195361Srstrong@cs.ucsd.edu else: 3205369Ssaidi@eecs.umich.edu when, period = options.take_checkpoints.split(",", 1) 3215369Ssaidi@eecs.umich.edu when = int(when) 3225369Ssaidi@eecs.umich.edu period = int(period) 3235369Ssaidi@eecs.umich.edu 3245361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when) 3255361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3265361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when - m5.curTick()) 3275361Srstrong@cs.ucsd.edu 3285361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3297525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3305361Srstrong@cs.ucsd.edu num_checkpoints += 1 3315361Srstrong@cs.ucsd.edu 3325361Srstrong@cs.ucsd.edu sim_ticks = when 3335361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3345361Srstrong@cs.ucsd.edu while num_checkpoints < max_checkpoints and \ 3355361Srstrong@cs.ucsd.edu exit_event.getCause() == "simulate() limit reached": 3365361Srstrong@cs.ucsd.edu if (sim_ticks + period) > maxtick: 3375361Srstrong@cs.ucsd.edu exit_event = m5.simulate(maxtick - sim_ticks) 3385361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause() 3395361Srstrong@cs.ucsd.edu break 3405361Srstrong@cs.ucsd.edu else: 3415361Srstrong@cs.ucsd.edu exit_event = m5.simulate(period) 3425361Srstrong@cs.ucsd.edu sim_ticks += period 3435361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3445361Srstrong@cs.ucsd.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 3455361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3467525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3475361Srstrong@cs.ucsd.edu num_checkpoints += 1 3485361Srstrong@cs.ucsd.edu 3495361Srstrong@cs.ucsd.edu if exit_event.getCause() != "simulate() limit reached": 3505361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3515361Srstrong@cs.ucsd.edu 3525361Srstrong@cs.ucsd.edu else: # no checkpoints being taken via this script 3535361Srstrong@cs.ucsd.edu if options.fast_forward: 3545361Srstrong@cs.ucsd.edu m5.stats.reset() 3555361Srstrong@cs.ucsd.edu print "**** REAL SIMULATION ****" 3563395Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick) 3573395Shsul@eecs.umich.edu 3583395Shsul@eecs.umich.edu while exit_event.getCause() == "checkpoint": 3597525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3603395Shsul@eecs.umich.edu num_checkpoints += 1 3613395Shsul@eecs.umich.edu if num_checkpoints == max_checkpoints: 3625361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3633395Shsul@eecs.umich.edu break 3643395Shsul@eecs.umich.edu 3653511Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 3663395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 3673395Shsul@eecs.umich.edu 3683395Shsul@eecs.umich.edu if exit_cause == '': 3693395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 3707766Sgblack@eecs.umich.edu print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 3713395Shsul@eecs.umich.edu 3726776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 3737525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3746776SBrad.Beckmann@amd.com 375