Simulation.py revision 7530
15347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 23395Shsul@eecs.umich.edu# All rights reserved. 33395Shsul@eecs.umich.edu# 43395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 63395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133395Shsul@eecs.umich.edu# this software without specific prior written permission. 143395Shsul@eecs.umich.edu# 153395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263395Shsul@eecs.umich.edu# 273395Shsul@eecs.umich.edu# Authors: Lisa Hsu 283395Shsul@eecs.umich.edu 293395Shsul@eecs.umich.edufrom os import getcwd 303509Shsul@eecs.umich.edufrom os.path import join as joinpath 316654Snate@binkert.org 323395Shsul@eecs.umich.eduimport m5 336654Snate@binkert.orgfrom m5.defines import buildEnv 343395Shsul@eecs.umich.edufrom m5.objects import * 356654Snate@binkert.orgfrom m5.util import * 366654Snate@binkert.org 376654Snate@binkert.orgaddToPath('../common') 383395Shsul@eecs.umich.edu 393481Shsul@eecs.umich.edudef setCPUClass(options): 403481Shsul@eecs.umich.edu 413481Shsul@eecs.umich.edu atomic = False 423481Shsul@eecs.umich.edu if options.timing: 435347Ssaidi@eecs.umich.edu class TmpClass(TimingSimpleCPU): pass 443481Shsul@eecs.umich.edu elif options.detailed: 453681Sktlim@umich.edu if not options.caches: 463681Sktlim@umich.edu print "O3 CPU must be used with caches" 473681Sktlim@umich.edu sys.exit(1) 485347Ssaidi@eecs.umich.edu class TmpClass(DerivO3CPU): pass 495869Sksewell@umich.edu elif options.inorder: 505869Sksewell@umich.edu if not options.caches: 515869Sksewell@umich.edu print "InOrder CPU must be used with caches" 525869Sksewell@umich.edu sys.exit(1) 535869Sksewell@umich.edu class TmpClass(InOrderCPU): pass 543481Shsul@eecs.umich.edu else: 555347Ssaidi@eecs.umich.edu class TmpClass(AtomicSimpleCPU): pass 563481Shsul@eecs.umich.edu atomic = True 573481Shsul@eecs.umich.edu 583481Shsul@eecs.umich.edu CPUClass = None 593481Shsul@eecs.umich.edu test_mem_mode = 'atomic' 603481Shsul@eecs.umich.edu 613481Shsul@eecs.umich.edu if not atomic: 625369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None or options.fast_forward: 633481Shsul@eecs.umich.edu CPUClass = TmpClass 645347Ssaidi@eecs.umich.edu class TmpClass(AtomicSimpleCPU): pass 653481Shsul@eecs.umich.edu else: 663481Shsul@eecs.umich.edu test_mem_mode = 'timing' 673481Shsul@eecs.umich.edu 683481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 693481Shsul@eecs.umich.edu 703481Shsul@eecs.umich.edu 713481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 723395Shsul@eecs.umich.edu if options.maxtick: 733395Shsul@eecs.umich.edu maxtick = options.maxtick 743395Shsul@eecs.umich.edu elif options.maxtime: 754167Sbinkertn@umich.edu simtime = m5.ticks.seconds(simtime) 763395Shsul@eecs.umich.edu print "simulating for: ", simtime 773395Shsul@eecs.umich.edu maxtick = simtime 783395Shsul@eecs.umich.edu else: 793511Shsul@eecs.umich.edu maxtick = m5.MaxTick 803395Shsul@eecs.umich.edu 813395Shsul@eecs.umich.edu if options.checkpoint_dir: 823395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 835211Ssaidi@eecs.umich.edu elif m5.options.outdir: 845211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 853395Shsul@eecs.umich.edu else: 863395Shsul@eecs.umich.edu cptdir = getcwd() 873395Shsul@eecs.umich.edu 885370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 896654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 905370Ssaidi@eecs.umich.edu 915371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 926654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 935370Ssaidi@eecs.umich.edu 943395Shsul@eecs.umich.edu np = options.num_cpus 953395Shsul@eecs.umich.edu max_checkpoints = options.max_checkpoints 963481Shsul@eecs.umich.edu switch_cpus = None 973481Shsul@eecs.umich.edu 986144Sksewell@umich.edu if options.prog_intvl: 996144Sksewell@umich.edu for i in xrange(np): 1006144Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_intvl 1016144Sksewell@umich.edu 1026641Sksewell@umich.edu if options.maxinsts: 1036641Sksewell@umich.edu for i in xrange(np): 1046641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 1056641Sksewell@umich.edu 1063481Shsul@eecs.umich.edu if cpu_class: 1073481Shsul@eecs.umich.edu switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 1083481Shsul@eecs.umich.edu for i in xrange(np)] 1093481Shsul@eecs.umich.edu 1103481Shsul@eecs.umich.edu for i in xrange(np): 1115361Srstrong@cs.ucsd.edu if options.fast_forward: 1125369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1133481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1146654Snate@binkert.org if not buildEnv['FULL_SYSTEM']: 1153481Shsul@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1163481Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 1175369Ssaidi@eecs.umich.edu # simulation period 1185369Ssaidi@eecs.umich.edu if options.max_inst: 1195369Ssaidi@eecs.umich.edu switch_cpus[i].max_insts_any_thread = options.max_inst 1203481Shsul@eecs.umich.edu 1215311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 1223481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1233395Shsul@eecs.umich.edu 1243395Shsul@eecs.umich.edu if options.standard_switch: 1253395Shsul@eecs.umich.edu switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 1263395Shsul@eecs.umich.edu for i in xrange(np)] 1273478Shsul@eecs.umich.edu switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 1283395Shsul@eecs.umich.edu for i in xrange(np)] 1293478Shsul@eecs.umich.edu 1303395Shsul@eecs.umich.edu for i in xrange(np): 1313395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1323478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 1336654Snate@binkert.org if not buildEnv['FULL_SYSTEM']: 1343395Shsul@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1353478Shsul@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 1363395Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 1373478Shsul@eecs.umich.edu switch_cpus_1[i].clock = testsys.cpu[0].clock 1383480Shsul@eecs.umich.edu 1395361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 1405369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 1415361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1425361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 1435361Srstrong@cs.ucsd.edu elif options.fast_forward: 1445369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1455361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 1465361Srstrong@cs.ucsd.edu elif options.simpoint: 1475378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 1486654Snate@binkert.org fatal('simpoint not found') 1495361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 1505361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 1515361Srstrong@cs.ucsd.edu # No distance specified, just switch 1525361Srstrong@cs.ucsd.edu else: 1535361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1545361Srstrong@cs.ucsd.edu 1555361Srstrong@cs.ucsd.edu # warmup period 1565361Srstrong@cs.ucsd.edu if options.warmup_insts: 1575361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 1585361Srstrong@cs.ucsd.edu 1595361Srstrong@cs.ucsd.edu # simulation period 1605353Svilas.sridharan@gmail.com if options.max_inst: 1615353Svilas.sridharan@gmail.com switch_cpus_1[i].max_insts_any_thread = options.max_inst 1625353Svilas.sridharan@gmail.com 1633514Sktlim@umich.edu if not options.caches: 1643481Shsul@eecs.umich.edu # O3 CPU must have a cache to work. 1656107Ssteve.reinhardt@amd.com print "O3 CPU must be used with caches" 1666107Ssteve.reinhardt@amd.com sys.exit(1) 1673395Shsul@eecs.umich.edu 1683514Sktlim@umich.edu testsys.switch_cpus = switch_cpus 1693514Sktlim@umich.edu testsys.switch_cpus_1 = switch_cpus_1 1703395Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1713478Shsul@eecs.umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 1723395Shsul@eecs.umich.edu 1735361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 1745369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 1755361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 1765361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 1775361Srstrong@cs.ucsd.edu # Set an instruction break point 1785361Srstrong@cs.ucsd.edu if options.simpoint: 1795361Srstrong@cs.ucsd.edu for i in xrange(np): 1805378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 1816654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 1825369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 1835361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 1845361Srstrong@cs.ucsd.edu # used for output below 1855361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 1865361Srstrong@cs.ucsd.edu else: 1875361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 1885361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 1895361Srstrong@cs.ucsd.edu # for the upcoming simulation 1905361Srstrong@cs.ucsd.edu for i in xrange(np): 1915361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 1925361Srstrong@cs.ucsd.edu 1937525Ssteve.reinhardt@amd.com m5.instantiate() 1943395Shsul@eecs.umich.edu 1955369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 1965361Srstrong@cs.ucsd.edu from os.path import isdir, exists 1973395Shsul@eecs.umich.edu from os import listdir 1983395Shsul@eecs.umich.edu import re 1993395Shsul@eecs.umich.edu 2003395Shsul@eecs.umich.edu if not isdir(cptdir): 2016654Snate@binkert.org fatal("checkpoint dir %s does not exist!", cptdir) 2023395Shsul@eecs.umich.edu 2037530Ssteve.reinhardt@amd.com if options.at_instruction or options.simpoint: 2047530Ssteve.reinhardt@amd.com inst = options.checkpoint_restore 2057530Ssteve.reinhardt@amd.com if options.simpoint: 2067530Ssteve.reinhardt@amd.com # assume workload 0 has the simpoint 2077530Ssteve.reinhardt@amd.com if testsys.cpu[0].workload[0].simpoint == 0: 2087530Ssteve.reinhardt@amd.com fatal('Unable to find simpoint') 2097530Ssteve.reinhardt@amd.com inst += int(testsys.cpu[0].workload[0].simpoint) 2107530Ssteve.reinhardt@amd.com 2117530Ssteve.reinhardt@amd.com checkpoint_dir = joinpath(cptdir, 2127530Ssteve.reinhardt@amd.com "cpt.%s.%s" % (options.bench, inst)) 2135361Srstrong@cs.ucsd.edu if not exists(checkpoint_dir): 2146654Snate@binkert.org fatal("Unable to find checkpoint directory %s", checkpoint_dir) 2153395Shsul@eecs.umich.edu 2165361Srstrong@cs.ucsd.edu print "Restoring checkpoint ..." 2177525Ssteve.reinhardt@amd.com m5.restoreCheckpoint(checkpoint_dir) 2185361Srstrong@cs.ucsd.edu print "Done." 2195361Srstrong@cs.ucsd.edu else: 2205361Srstrong@cs.ucsd.edu dirs = listdir(cptdir) 2215361Srstrong@cs.ucsd.edu expr = re.compile('cpt\.([0-9]*)') 2225361Srstrong@cs.ucsd.edu cpts = [] 2235361Srstrong@cs.ucsd.edu for dir in dirs: 2245361Srstrong@cs.ucsd.edu match = expr.match(dir) 2255361Srstrong@cs.ucsd.edu if match: 2265361Srstrong@cs.ucsd.edu cpts.append(match.group(1)) 2273999Ssaidi@eecs.umich.edu 2285361Srstrong@cs.ucsd.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 2295361Srstrong@cs.ucsd.edu 2305361Srstrong@cs.ucsd.edu cpt_num = options.checkpoint_restore 2315361Srstrong@cs.ucsd.edu 2325361Srstrong@cs.ucsd.edu if cpt_num > len(cpts): 2336654Snate@binkert.org fatal('Checkpoint %d not found', cpt_num) 2345361Srstrong@cs.ucsd.edu 2355361Srstrong@cs.ucsd.edu ## Adjust max tick based on our starting tick 2365361Srstrong@cs.ucsd.edu maxtick = maxtick - int(cpts[cpt_num - 1]) 2375361Srstrong@cs.ucsd.edu 2385361Srstrong@cs.ucsd.edu ## Restore the checkpoint 2397525Ssteve.reinhardt@amd.com m5.restoreCheckpoint(joinpath(cptdir, 2407525Ssteve.reinhardt@amd.com "cpt.%s" % cpts[cpt_num - 1])) 2413395Shsul@eecs.umich.edu 2423481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 2435361Srstrong@cs.ucsd.edu if options.standard_switch: 2445361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2455361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2465361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2475361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 2485361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2495361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2505361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2515361Srstrong@cs.ucsd.edu else: 2525361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 2535361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 2545361Srstrong@cs.ucsd.edu print "Switched CPUS @ cycle = %s" % (m5.curTick()) 2553395Shsul@eecs.umich.edu 2565361Srstrong@cs.ucsd.edu # when you change to Timing (or Atomic), you halt the system 2575361Srstrong@cs.ucsd.edu # given as argument. When you are finished with the system 2585361Srstrong@cs.ucsd.edu # changes (including switchCpus), you must resume the system 2595361Srstrong@cs.ucsd.edu # manually. You DON'T need to resume after just switching 2605361Srstrong@cs.ucsd.edu # CPUs if you haven't changed anything on the system level. 2613395Shsul@eecs.umich.edu 2623395Shsul@eecs.umich.edu m5.changeToTiming(testsys) 2633395Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list) 2643395Shsul@eecs.umich.edu m5.resume(testsys) 2653395Shsul@eecs.umich.edu 2663481Shsul@eecs.umich.edu if options.standard_switch: 2675361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 2685361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 2695361Srstrong@cs.ucsd.edu 2705361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 2715361Srstrong@cs.ucsd.edu if options.warmup_insts: 2725361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2735361Srstrong@cs.ucsd.edu else: 2745353Svilas.sridharan@gmail.com exit_event = m5.simulate(options.warmup) 2755361Srstrong@cs.ucsd.edu print "Switching CPUS @ cycle = %s" % (m5.curTick()) 2765361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 2775361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 2785072Ssaidi@eecs.umich.edu m5.drain(testsys) 2793481Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list1) 2805072Ssaidi@eecs.umich.edu m5.resume(testsys) 2813395Shsul@eecs.umich.edu 2823395Shsul@eecs.umich.edu num_checkpoints = 0 2833395Shsul@eecs.umich.edu exit_cause = '' 2843395Shsul@eecs.umich.edu 2857489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 2867489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 2877489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 2887489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 2897489Ssteve.reinhardt@amd.com if options.take_checkpoints and options.checkpoint_restore: 2907489Ssteve.reinhardt@amd.com if m5.options.outdir: 2917489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 2927489Ssteve.reinhardt@amd.com else: 2937489Ssteve.reinhardt@amd.com cptdir = getcwd() 2947489Ssteve.reinhardt@amd.com 2955361Srstrong@cs.ucsd.edu # Checkpoints being taken via the command line at <when> and at 2965361Srstrong@cs.ucsd.edu # subsequent periods of <period>. Checkpoint instructions 2975361Srstrong@cs.ucsd.edu # received from the benchmark running are ignored and skipped in 2985361Srstrong@cs.ucsd.edu # favor of command line checkpoint instructions. 2995369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 3005361Srstrong@cs.ucsd.edu if options.at_instruction or options.simpoint: 3015369Ssaidi@eecs.umich.edu checkpoint_inst = int(options.take_checkpoints) 3023395Shsul@eecs.umich.edu 3035361Srstrong@cs.ucsd.edu # maintain correct offset if we restored from some instruction 3045369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 3055361Srstrong@cs.ucsd.edu checkpoint_inst += options.checkpoint_restore 3063395Shsul@eecs.umich.edu 3075361Srstrong@cs.ucsd.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 3085361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3095361Srstrong@cs.ucsd.edu print "exit cause = %s" % (exit_event.getCause()) 3103395Shsul@eecs.umich.edu 3115361Srstrong@cs.ucsd.edu # skip checkpoint instructions should they exist 3125361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3135361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3143999Ssaidi@eecs.umich.edu 3155361Srstrong@cs.ucsd.edu if exit_event.getCause() == \ 3165361Srstrong@cs.ucsd.edu "a thread reached the max instruction count": 3177525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 3185361Srstrong@cs.ucsd.edu (options.bench, checkpoint_inst))) 3195361Srstrong@cs.ucsd.edu print "Checkpoint written." 3205361Srstrong@cs.ucsd.edu num_checkpoints += 1 3213999Ssaidi@eecs.umich.edu 3225361Srstrong@cs.ucsd.edu if exit_event.getCause() == "user interrupt received": 3235361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3245361Srstrong@cs.ucsd.edu else: 3255369Ssaidi@eecs.umich.edu when, period = options.take_checkpoints.split(",", 1) 3265369Ssaidi@eecs.umich.edu when = int(when) 3275369Ssaidi@eecs.umich.edu period = int(period) 3285369Ssaidi@eecs.umich.edu 3295361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when) 3305361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3315361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when - m5.curTick()) 3325361Srstrong@cs.ucsd.edu 3335361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3347525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3355361Srstrong@cs.ucsd.edu num_checkpoints += 1 3365361Srstrong@cs.ucsd.edu 3375361Srstrong@cs.ucsd.edu sim_ticks = when 3385361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3395361Srstrong@cs.ucsd.edu while num_checkpoints < max_checkpoints and \ 3405361Srstrong@cs.ucsd.edu exit_event.getCause() == "simulate() limit reached": 3415361Srstrong@cs.ucsd.edu if (sim_ticks + period) > maxtick: 3425361Srstrong@cs.ucsd.edu exit_event = m5.simulate(maxtick - sim_ticks) 3435361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause() 3445361Srstrong@cs.ucsd.edu break 3455361Srstrong@cs.ucsd.edu else: 3465361Srstrong@cs.ucsd.edu exit_event = m5.simulate(period) 3475361Srstrong@cs.ucsd.edu sim_ticks += period 3485361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3495361Srstrong@cs.ucsd.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 3505361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3517525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3525361Srstrong@cs.ucsd.edu num_checkpoints += 1 3535361Srstrong@cs.ucsd.edu 3545361Srstrong@cs.ucsd.edu if exit_event.getCause() != "simulate() limit reached": 3555361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3565361Srstrong@cs.ucsd.edu 3575361Srstrong@cs.ucsd.edu else: # no checkpoints being taken via this script 3585361Srstrong@cs.ucsd.edu if options.fast_forward: 3595361Srstrong@cs.ucsd.edu m5.stats.reset() 3605361Srstrong@cs.ucsd.edu print "**** REAL SIMULATION ****" 3613395Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick) 3623395Shsul@eecs.umich.edu 3633395Shsul@eecs.umich.edu while exit_event.getCause() == "checkpoint": 3647525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3653395Shsul@eecs.umich.edu num_checkpoints += 1 3663395Shsul@eecs.umich.edu if num_checkpoints == max_checkpoints: 3675361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3683395Shsul@eecs.umich.edu break 3693395Shsul@eecs.umich.edu 3703511Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 3713395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 3723395Shsul@eecs.umich.edu 3733395Shsul@eecs.umich.edu if exit_cause == '': 3743395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 3753514Sktlim@umich.edu print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) 3763395Shsul@eecs.umich.edu 3776776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 3787525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3796776SBrad.Beckmann@amd.com 380