Simulation.py revision 5869
15347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 23395Shsul@eecs.umich.edu# All rights reserved. 33395Shsul@eecs.umich.edu# 43395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 63395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133395Shsul@eecs.umich.edu# this software without specific prior written permission. 143395Shsul@eecs.umich.edu# 153395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263395Shsul@eecs.umich.edu# 273395Shsul@eecs.umich.edu# Authors: Lisa Hsu 283395Shsul@eecs.umich.edu 293395Shsul@eecs.umich.edufrom os import getcwd 303509Shsul@eecs.umich.edufrom os.path import join as joinpath 313395Shsul@eecs.umich.eduimport m5 323395Shsul@eecs.umich.edufrom m5.objects import * 333395Shsul@eecs.umich.edum5.AddToPath('../common') 343448Shsul@eecs.umich.edufrom Caches import L1Cache 353395Shsul@eecs.umich.edu 363481Shsul@eecs.umich.edudef setCPUClass(options): 373481Shsul@eecs.umich.edu 383481Shsul@eecs.umich.edu atomic = False 393481Shsul@eecs.umich.edu if options.timing: 405347Ssaidi@eecs.umich.edu class TmpClass(TimingSimpleCPU): pass 413481Shsul@eecs.umich.edu elif options.detailed: 423681Sktlim@umich.edu if not options.caches: 433681Sktlim@umich.edu print "O3 CPU must be used with caches" 443681Sktlim@umich.edu sys.exit(1) 455347Ssaidi@eecs.umich.edu class TmpClass(DerivO3CPU): pass 465869Sksewell@umich.edu elif options.inorder: 475869Sksewell@umich.edu if not options.caches: 485869Sksewell@umich.edu print "InOrder CPU must be used with caches" 495869Sksewell@umich.edu sys.exit(1) 505869Sksewell@umich.edu class TmpClass(InOrderCPU): pass 513481Shsul@eecs.umich.edu else: 525347Ssaidi@eecs.umich.edu class TmpClass(AtomicSimpleCPU): pass 533481Shsul@eecs.umich.edu atomic = True 543481Shsul@eecs.umich.edu 553481Shsul@eecs.umich.edu CPUClass = None 563481Shsul@eecs.umich.edu test_mem_mode = 'atomic' 573481Shsul@eecs.umich.edu 583481Shsul@eecs.umich.edu if not atomic: 595369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None or options.fast_forward: 603481Shsul@eecs.umich.edu CPUClass = TmpClass 615347Ssaidi@eecs.umich.edu class TmpClass(AtomicSimpleCPU): pass 623481Shsul@eecs.umich.edu else: 633481Shsul@eecs.umich.edu test_mem_mode = 'timing' 643481Shsul@eecs.umich.edu 653481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 663481Shsul@eecs.umich.edu 673481Shsul@eecs.umich.edu 683481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 693395Shsul@eecs.umich.edu if options.maxtick: 703395Shsul@eecs.umich.edu maxtick = options.maxtick 713395Shsul@eecs.umich.edu elif options.maxtime: 724167Sbinkertn@umich.edu simtime = m5.ticks.seconds(simtime) 733395Shsul@eecs.umich.edu print "simulating for: ", simtime 743395Shsul@eecs.umich.edu maxtick = simtime 753395Shsul@eecs.umich.edu else: 763511Shsul@eecs.umich.edu maxtick = m5.MaxTick 773395Shsul@eecs.umich.edu 783395Shsul@eecs.umich.edu if options.checkpoint_dir: 793395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 805211Ssaidi@eecs.umich.edu elif m5.options.outdir: 815211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 823395Shsul@eecs.umich.edu else: 833395Shsul@eecs.umich.edu cptdir = getcwd() 843395Shsul@eecs.umich.edu 855370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 865822Ssaidi@eecs.umich.edu m5.fatal("Error: Can't specify both --fast-forward and --checkpoint-restore") 875370Ssaidi@eecs.umich.edu 885371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 895822Ssaidi@eecs.umich.edu m5.fatal("Error: Must specify --caches when using --standard-switch") 905370Ssaidi@eecs.umich.edu 913395Shsul@eecs.umich.edu np = options.num_cpus 923395Shsul@eecs.umich.edu max_checkpoints = options.max_checkpoints 933481Shsul@eecs.umich.edu switch_cpus = None 943481Shsul@eecs.umich.edu 953481Shsul@eecs.umich.edu if cpu_class: 963481Shsul@eecs.umich.edu switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 973481Shsul@eecs.umich.edu for i in xrange(np)] 983481Shsul@eecs.umich.edu 993481Shsul@eecs.umich.edu for i in xrange(np): 1005361Srstrong@cs.ucsd.edu if options.fast_forward: 1015369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1023481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1033481Shsul@eecs.umich.edu if not m5.build_env['FULL_SYSTEM']: 1043481Shsul@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1053481Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 1065369Ssaidi@eecs.umich.edu # simulation period 1075369Ssaidi@eecs.umich.edu if options.max_inst: 1085369Ssaidi@eecs.umich.edu switch_cpus[i].max_insts_any_thread = options.max_inst 1093481Shsul@eecs.umich.edu 1105311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 1113481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1123395Shsul@eecs.umich.edu 1133395Shsul@eecs.umich.edu if options.standard_switch: 1143395Shsul@eecs.umich.edu switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 1153395Shsul@eecs.umich.edu for i in xrange(np)] 1163478Shsul@eecs.umich.edu switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 1173395Shsul@eecs.umich.edu for i in xrange(np)] 1183478Shsul@eecs.umich.edu 1193395Shsul@eecs.umich.edu for i in xrange(np): 1203395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1213478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 1223395Shsul@eecs.umich.edu if not m5.build_env['FULL_SYSTEM']: 1233395Shsul@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1243478Shsul@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 1253395Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 1263478Shsul@eecs.umich.edu switch_cpus_1[i].clock = testsys.cpu[0].clock 1273480Shsul@eecs.umich.edu 1285361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 1295369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 1305361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1315361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 1325361Srstrong@cs.ucsd.edu elif options.fast_forward: 1335369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1345361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 1355361Srstrong@cs.ucsd.edu elif options.simpoint: 1365378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 1375822Ssaidi@eecs.umich.edu m5.fatal('simpoint not found') 1385361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 1395361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 1405361Srstrong@cs.ucsd.edu # No distance specified, just switch 1415361Srstrong@cs.ucsd.edu else: 1425361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1435361Srstrong@cs.ucsd.edu 1445361Srstrong@cs.ucsd.edu # warmup period 1455361Srstrong@cs.ucsd.edu if options.warmup_insts: 1465361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 1475361Srstrong@cs.ucsd.edu 1485361Srstrong@cs.ucsd.edu # simulation period 1495353Svilas.sridharan@gmail.com if options.max_inst: 1505353Svilas.sridharan@gmail.com switch_cpus_1[i].max_insts_any_thread = options.max_inst 1515353Svilas.sridharan@gmail.com 1523514Sktlim@umich.edu if not options.caches: 1533481Shsul@eecs.umich.edu # O3 CPU must have a cache to work. 1543480Shsul@eecs.umich.edu switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 1553480Shsul@eecs.umich.edu L1Cache(size = '64kB')) 1563480Shsul@eecs.umich.edu switch_cpus_1[i].connectMemPorts(testsys.membus) 1573395Shsul@eecs.umich.edu 1583514Sktlim@umich.edu testsys.switch_cpus = switch_cpus 1593514Sktlim@umich.edu testsys.switch_cpus_1 = switch_cpus_1 1603395Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1613478Shsul@eecs.umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 1623395Shsul@eecs.umich.edu 1635361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 1645369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 1655361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 1665361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 1675361Srstrong@cs.ucsd.edu # Set an instruction break point 1685361Srstrong@cs.ucsd.edu if options.simpoint: 1695361Srstrong@cs.ucsd.edu for i in xrange(np): 1705378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 1715822Ssaidi@eecs.umich.edu m5.fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 1725369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 1735361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 1745361Srstrong@cs.ucsd.edu # used for output below 1755361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 1765361Srstrong@cs.ucsd.edu else: 1775361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 1785361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 1795361Srstrong@cs.ucsd.edu # for the upcoming simulation 1805361Srstrong@cs.ucsd.edu for i in xrange(np): 1815361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 1825361Srstrong@cs.ucsd.edu 1833395Shsul@eecs.umich.edu m5.instantiate(root) 1843395Shsul@eecs.umich.edu 1855369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 1865361Srstrong@cs.ucsd.edu from os.path import isdir, exists 1873395Shsul@eecs.umich.edu from os import listdir 1883395Shsul@eecs.umich.edu import re 1893395Shsul@eecs.umich.edu 1903395Shsul@eecs.umich.edu if not isdir(cptdir): 1915822Ssaidi@eecs.umich.edu m5.fatal("checkpoint dir %s does not exist!", cptdir) 1923395Shsul@eecs.umich.edu 1935361Srstrong@cs.ucsd.edu if options.at_instruction: 1945361Srstrong@cs.ucsd.edu checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % \ 1955361Srstrong@cs.ucsd.edu (options.bench, options.checkpoint_restore)) 1965361Srstrong@cs.ucsd.edu if not exists(checkpoint_dir): 1975822Ssaidi@eecs.umich.edu m5.fatal("Unable to find checkpoint directory %s", 1985361Srstrong@cs.ucsd.edu checkpoint_dir) 1993395Shsul@eecs.umich.edu 2005361Srstrong@cs.ucsd.edu print "Restoring checkpoint ..." 2015361Srstrong@cs.ucsd.edu m5.restoreCheckpoint(root, checkpoint_dir) 2025361Srstrong@cs.ucsd.edu print "Done." 2035361Srstrong@cs.ucsd.edu elif options.simpoint: 2045361Srstrong@cs.ucsd.edu # assume workload 0 has the simpoint 2055378Ssaidi@eecs.umich.edu if testsys.cpu[0].workload[0].simpoint == 0: 2065822Ssaidi@eecs.umich.edu m5.fatal('Unable to find simpoint') 2073395Shsul@eecs.umich.edu 2085361Srstrong@cs.ucsd.edu options.checkpoint_restore += \ 2095369Ssaidi@eecs.umich.edu int(testsys.cpu[0].workload[0].simpoint) 2103395Shsul@eecs.umich.edu 2115361Srstrong@cs.ucsd.edu checkpoint_dir = joinpath(cptdir, "cpt.%s.%d" % \ 2125361Srstrong@cs.ucsd.edu (options.bench, options.checkpoint_restore)) 2135361Srstrong@cs.ucsd.edu if not exists(checkpoint_dir): 2145822Ssaidi@eecs.umich.edu m5.fatal("Unable to find checkpoint directory %s.%s", 2155822Ssaidi@eecs.umich.edu options.bench, options.checkpoint_restore) 2163395Shsul@eecs.umich.edu 2175361Srstrong@cs.ucsd.edu print "Restoring checkpoint ..." 2185361Srstrong@cs.ucsd.edu m5.restoreCheckpoint(root,checkpoint_dir) 2195361Srstrong@cs.ucsd.edu print "Done." 2205361Srstrong@cs.ucsd.edu else: 2215361Srstrong@cs.ucsd.edu dirs = listdir(cptdir) 2225361Srstrong@cs.ucsd.edu expr = re.compile('cpt\.([0-9]*)') 2235361Srstrong@cs.ucsd.edu cpts = [] 2245361Srstrong@cs.ucsd.edu for dir in dirs: 2255361Srstrong@cs.ucsd.edu match = expr.match(dir) 2265361Srstrong@cs.ucsd.edu if match: 2275361Srstrong@cs.ucsd.edu cpts.append(match.group(1)) 2283999Ssaidi@eecs.umich.edu 2295361Srstrong@cs.ucsd.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 2305361Srstrong@cs.ucsd.edu 2315361Srstrong@cs.ucsd.edu cpt_num = options.checkpoint_restore 2325361Srstrong@cs.ucsd.edu 2335361Srstrong@cs.ucsd.edu if cpt_num > len(cpts): 2345822Ssaidi@eecs.umich.edu m5.fatal('Checkpoint %d not found', cpt_num) 2355361Srstrong@cs.ucsd.edu 2365361Srstrong@cs.ucsd.edu ## Adjust max tick based on our starting tick 2375361Srstrong@cs.ucsd.edu maxtick = maxtick - int(cpts[cpt_num - 1]) 2385361Srstrong@cs.ucsd.edu 2395361Srstrong@cs.ucsd.edu ## Restore the checkpoint 2405361Srstrong@cs.ucsd.edu m5.restoreCheckpoint(root, 2415361Srstrong@cs.ucsd.edu joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1])) 2423395Shsul@eecs.umich.edu 2433481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 2445361Srstrong@cs.ucsd.edu if options.standard_switch: 2455361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2465361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2475361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2485361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 2495361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2505361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2515361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2525361Srstrong@cs.ucsd.edu else: 2535361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 2545361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 2555361Srstrong@cs.ucsd.edu print "Switched CPUS @ cycle = %s" % (m5.curTick()) 2563395Shsul@eecs.umich.edu 2575361Srstrong@cs.ucsd.edu # when you change to Timing (or Atomic), you halt the system 2585361Srstrong@cs.ucsd.edu # given as argument. When you are finished with the system 2595361Srstrong@cs.ucsd.edu # changes (including switchCpus), you must resume the system 2605361Srstrong@cs.ucsd.edu # manually. You DON'T need to resume after just switching 2615361Srstrong@cs.ucsd.edu # CPUs if you haven't changed anything on the system level. 2623395Shsul@eecs.umich.edu 2633395Shsul@eecs.umich.edu m5.changeToTiming(testsys) 2643395Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list) 2653395Shsul@eecs.umich.edu m5.resume(testsys) 2663395Shsul@eecs.umich.edu 2673481Shsul@eecs.umich.edu if options.standard_switch: 2685361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 2695361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 2705361Srstrong@cs.ucsd.edu 2715361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 2725361Srstrong@cs.ucsd.edu if options.warmup_insts: 2735361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2745361Srstrong@cs.ucsd.edu else: 2755353Svilas.sridharan@gmail.com exit_event = m5.simulate(options.warmup) 2765361Srstrong@cs.ucsd.edu print "Switching CPUS @ cycle = %s" % (m5.curTick()) 2775361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 2785361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 2795072Ssaidi@eecs.umich.edu m5.drain(testsys) 2803481Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list1) 2815072Ssaidi@eecs.umich.edu m5.resume(testsys) 2823395Shsul@eecs.umich.edu 2833395Shsul@eecs.umich.edu num_checkpoints = 0 2843395Shsul@eecs.umich.edu exit_cause = '' 2853395Shsul@eecs.umich.edu 2865361Srstrong@cs.ucsd.edu # Checkpoints being taken via the command line at <when> and at 2875361Srstrong@cs.ucsd.edu # subsequent periods of <period>. Checkpoint instructions 2885361Srstrong@cs.ucsd.edu # received from the benchmark running are ignored and skipped in 2895361Srstrong@cs.ucsd.edu # favor of command line checkpoint instructions. 2905369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 2915361Srstrong@cs.ucsd.edu if options.at_instruction or options.simpoint: 2925369Ssaidi@eecs.umich.edu checkpoint_inst = int(options.take_checkpoints) 2933395Shsul@eecs.umich.edu 2945361Srstrong@cs.ucsd.edu # maintain correct offset if we restored from some instruction 2955369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 2965361Srstrong@cs.ucsd.edu checkpoint_inst += options.checkpoint_restore 2973395Shsul@eecs.umich.edu 2985361Srstrong@cs.ucsd.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 2995361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3005361Srstrong@cs.ucsd.edu print "exit cause = %s" % (exit_event.getCause()) 3013395Shsul@eecs.umich.edu 3025361Srstrong@cs.ucsd.edu # skip checkpoint instructions should they exist 3035361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3045361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3053999Ssaidi@eecs.umich.edu 3065361Srstrong@cs.ucsd.edu if exit_event.getCause() == \ 3075361Srstrong@cs.ucsd.edu "a thread reached the max instruction count": 3085361Srstrong@cs.ucsd.edu m5.checkpoint(root, joinpath(cptdir, "cpt.%s.%d" % \ 3095361Srstrong@cs.ucsd.edu (options.bench, checkpoint_inst))) 3105361Srstrong@cs.ucsd.edu print "Checkpoint written." 3115361Srstrong@cs.ucsd.edu num_checkpoints += 1 3123999Ssaidi@eecs.umich.edu 3135361Srstrong@cs.ucsd.edu if exit_event.getCause() == "user interrupt received": 3145361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3155361Srstrong@cs.ucsd.edu else: 3165369Ssaidi@eecs.umich.edu when, period = options.take_checkpoints.split(",", 1) 3175369Ssaidi@eecs.umich.edu when = int(when) 3185369Ssaidi@eecs.umich.edu period = int(period) 3195369Ssaidi@eecs.umich.edu 3205361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when) 3215361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3225361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when - m5.curTick()) 3235361Srstrong@cs.ucsd.edu 3245361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3255361Srstrong@cs.ucsd.edu m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) 3265361Srstrong@cs.ucsd.edu num_checkpoints += 1 3275361Srstrong@cs.ucsd.edu 3285361Srstrong@cs.ucsd.edu sim_ticks = when 3295361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3305361Srstrong@cs.ucsd.edu while num_checkpoints < max_checkpoints and \ 3315361Srstrong@cs.ucsd.edu exit_event.getCause() == "simulate() limit reached": 3325361Srstrong@cs.ucsd.edu if (sim_ticks + period) > maxtick: 3335361Srstrong@cs.ucsd.edu exit_event = m5.simulate(maxtick - sim_ticks) 3345361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause() 3355361Srstrong@cs.ucsd.edu break 3365361Srstrong@cs.ucsd.edu else: 3375361Srstrong@cs.ucsd.edu exit_event = m5.simulate(period) 3385361Srstrong@cs.ucsd.edu sim_ticks += period 3395361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3405361Srstrong@cs.ucsd.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 3415361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3425361Srstrong@cs.ucsd.edu m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) 3435361Srstrong@cs.ucsd.edu num_checkpoints += 1 3445361Srstrong@cs.ucsd.edu 3455361Srstrong@cs.ucsd.edu if exit_event.getCause() != "simulate() limit reached": 3465361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3475361Srstrong@cs.ucsd.edu 3485361Srstrong@cs.ucsd.edu else: # no checkpoints being taken via this script 3495361Srstrong@cs.ucsd.edu if options.fast_forward: 3505361Srstrong@cs.ucsd.edu m5.stats.reset() 3515361Srstrong@cs.ucsd.edu print "**** REAL SIMULATION ****" 3523395Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick) 3533395Shsul@eecs.umich.edu 3543395Shsul@eecs.umich.edu while exit_event.getCause() == "checkpoint": 3553509Shsul@eecs.umich.edu m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) 3563395Shsul@eecs.umich.edu num_checkpoints += 1 3573395Shsul@eecs.umich.edu if num_checkpoints == max_checkpoints: 3585361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3593395Shsul@eecs.umich.edu break 3603395Shsul@eecs.umich.edu 3613511Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 3623395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 3633395Shsul@eecs.umich.edu 3643395Shsul@eecs.umich.edu if exit_cause == '': 3653395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 3663514Sktlim@umich.edu print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) 3673395Shsul@eecs.umich.edu 368