Simulation.py revision 3511
13395Shsul@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 23395Shsul@eecs.umich.edu# All rights reserved. 33395Shsul@eecs.umich.edu# 43395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 63395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133395Shsul@eecs.umich.edu# this software without specific prior written permission. 143395Shsul@eecs.umich.edu# 153395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263395Shsul@eecs.umich.edu# 273395Shsul@eecs.umich.edu# Authors: Lisa Hsu 283395Shsul@eecs.umich.edu 293395Shsul@eecs.umich.edufrom os import getcwd 303509Shsul@eecs.umich.edufrom os.path import join as joinpath 313395Shsul@eecs.umich.eduimport m5 323395Shsul@eecs.umich.edufrom m5.objects import * 333395Shsul@eecs.umich.edum5.AddToPath('../common') 343448Shsul@eecs.umich.edufrom Caches import L1Cache 353395Shsul@eecs.umich.edu 363481Shsul@eecs.umich.edudef setCPUClass(options): 373481Shsul@eecs.umich.edu 383481Shsul@eecs.umich.edu atomic = False 393481Shsul@eecs.umich.edu if options.timing: 403481Shsul@eecs.umich.edu TmpClass = TimingSimpleCPU 413481Shsul@eecs.umich.edu elif options.detailed: 423481Shsul@eecs.umich.edu TmpClass = DerivO3CPU 433481Shsul@eecs.umich.edu else: 443481Shsul@eecs.umich.edu TmpClass = AtomicSimpleCPU 453481Shsul@eecs.umich.edu atomic = True 463481Shsul@eecs.umich.edu 473481Shsul@eecs.umich.edu CPUClass = None 483481Shsul@eecs.umich.edu test_mem_mode = 'atomic' 493481Shsul@eecs.umich.edu 503481Shsul@eecs.umich.edu if not atomic: 513481Shsul@eecs.umich.edu if options.checkpoint_restore: 523481Shsul@eecs.umich.edu CPUClass = TmpClass 533481Shsul@eecs.umich.edu TmpClass = AtomicSimpleCPU 543481Shsul@eecs.umich.edu else: 553481Shsul@eecs.umich.edu test_mem_mode = 'timing' 563481Shsul@eecs.umich.edu 573481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 583481Shsul@eecs.umich.edu 593481Shsul@eecs.umich.edu 603481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 613395Shsul@eecs.umich.edu if options.maxtick: 623395Shsul@eecs.umich.edu maxtick = options.maxtick 633395Shsul@eecs.umich.edu elif options.maxtime: 643395Shsul@eecs.umich.edu simtime = int(options.maxtime * root.clock.value) 653395Shsul@eecs.umich.edu print "simulating for: ", simtime 663395Shsul@eecs.umich.edu maxtick = simtime 673395Shsul@eecs.umich.edu else: 683511Shsul@eecs.umich.edu maxtick = m5.MaxTick 693395Shsul@eecs.umich.edu 703395Shsul@eecs.umich.edu if options.checkpoint_dir: 713395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 723395Shsul@eecs.umich.edu else: 733395Shsul@eecs.umich.edu cptdir = getcwd() 743395Shsul@eecs.umich.edu 753395Shsul@eecs.umich.edu np = options.num_cpus 763395Shsul@eecs.umich.edu max_checkpoints = options.max_checkpoints 773481Shsul@eecs.umich.edu switch_cpus = None 783481Shsul@eecs.umich.edu 793481Shsul@eecs.umich.edu if cpu_class: 803481Shsul@eecs.umich.edu switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 813481Shsul@eecs.umich.edu for i in xrange(np)] 823481Shsul@eecs.umich.edu 833481Shsul@eecs.umich.edu for i in xrange(np): 843481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 853481Shsul@eecs.umich.edu if not m5.build_env['FULL_SYSTEM']: 863481Shsul@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 873481Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 883481Shsul@eecs.umich.edu if options.caches: 893481Shsul@eecs.umich.edu switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 903481Shsul@eecs.umich.edu L1Cache(size = '64kB')) 913481Shsul@eecs.umich.edu switch_cpus[i].connectMemPorts(testsys.membus) 923481Shsul@eecs.umich.edu 933481Shsul@eecs.umich.edu root.switch_cpus = switch_cpus 943481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 953395Shsul@eecs.umich.edu 963395Shsul@eecs.umich.edu if options.standard_switch: 973395Shsul@eecs.umich.edu switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 983395Shsul@eecs.umich.edu for i in xrange(np)] 993478Shsul@eecs.umich.edu switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 1003395Shsul@eecs.umich.edu for i in xrange(np)] 1013478Shsul@eecs.umich.edu 1023395Shsul@eecs.umich.edu for i in xrange(np): 1033395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1043478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 1053395Shsul@eecs.umich.edu if not m5.build_env['FULL_SYSTEM']: 1063395Shsul@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1073478Shsul@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 1083395Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 1093478Shsul@eecs.umich.edu switch_cpus_1[i].clock = testsys.cpu[0].clock 1103480Shsul@eecs.umich.edu 1113395Shsul@eecs.umich.edu if options.caches: 1123395Shsul@eecs.umich.edu switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 1133395Shsul@eecs.umich.edu L1Cache(size = '64kB')) 1143481Shsul@eecs.umich.edu switch_cpus[i].connectMemPorts(testsys.membus) 1153481Shsul@eecs.umich.edu else: 1163481Shsul@eecs.umich.edu # O3 CPU must have a cache to work. 1173480Shsul@eecs.umich.edu switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 1183480Shsul@eecs.umich.edu L1Cache(size = '64kB')) 1193480Shsul@eecs.umich.edu switch_cpus_1[i].connectMemPorts(testsys.membus) 1203395Shsul@eecs.umich.edu 1213478Shsul@eecs.umich.edu 1223395Shsul@eecs.umich.edu root.switch_cpus = switch_cpus 1233478Shsul@eecs.umich.edu root.switch_cpus_1 = switch_cpus_1 1243395Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1253478Shsul@eecs.umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 1263395Shsul@eecs.umich.edu 1273395Shsul@eecs.umich.edu m5.instantiate(root) 1283395Shsul@eecs.umich.edu 1293395Shsul@eecs.umich.edu if options.checkpoint_restore: 1303395Shsul@eecs.umich.edu from os.path import isdir 1313395Shsul@eecs.umich.edu from os import listdir 1323395Shsul@eecs.umich.edu import re 1333395Shsul@eecs.umich.edu 1343395Shsul@eecs.umich.edu if not isdir(cptdir): 1353395Shsul@eecs.umich.edu m5.panic("checkpoint dir %s does not exist!" % cptdir) 1363395Shsul@eecs.umich.edu 1373395Shsul@eecs.umich.edu dirs = listdir(cptdir) 1383395Shsul@eecs.umich.edu expr = re.compile('cpt.([0-9]*)') 1393395Shsul@eecs.umich.edu cpts = [] 1403395Shsul@eecs.umich.edu for dir in dirs: 1413395Shsul@eecs.umich.edu match = expr.match(dir) 1423395Shsul@eecs.umich.edu if match: 1433395Shsul@eecs.umich.edu cpts.append(match.group(1)) 1443395Shsul@eecs.umich.edu 1453395Shsul@eecs.umich.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 1463395Shsul@eecs.umich.edu 1473395Shsul@eecs.umich.edu cpt_num = options.checkpoint_restore 1483395Shsul@eecs.umich.edu 1493395Shsul@eecs.umich.edu if cpt_num > len(cpts): 1503395Shsul@eecs.umich.edu m5.panic('Checkpoint %d not found' % cpt_num) 1513395Shsul@eecs.umich.edu 1523395Shsul@eecs.umich.edu m5.restoreCheckpoint(root, 1533509Shsul@eecs.umich.edu joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1])) 1543395Shsul@eecs.umich.edu 1553481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 1563395Shsul@eecs.umich.edu exit_event = m5.simulate(10000) 1573395Shsul@eecs.umich.edu 1583395Shsul@eecs.umich.edu ## when you change to Timing (or Atomic), you halt the system given 1593395Shsul@eecs.umich.edu ## as argument. When you are finished with the system changes 1603395Shsul@eecs.umich.edu ## (including switchCpus), you must resume the system manually. 1613395Shsul@eecs.umich.edu ## You DON'T need to resume after just switching CPUs if you haven't 1623395Shsul@eecs.umich.edu ## changed anything on the system level. 1633395Shsul@eecs.umich.edu 1643395Shsul@eecs.umich.edu m5.changeToTiming(testsys) 1653395Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list) 1663395Shsul@eecs.umich.edu m5.resume(testsys) 1673395Shsul@eecs.umich.edu 1683481Shsul@eecs.umich.edu if options.standard_switch: 1693481Shsul@eecs.umich.edu exit_event = m5.simulate(options.warmup) 1703481Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list1) 1713395Shsul@eecs.umich.edu 1723395Shsul@eecs.umich.edu num_checkpoints = 0 1733395Shsul@eecs.umich.edu exit_cause = '' 1743395Shsul@eecs.umich.edu 1753410Shsul@eecs.umich.edu ## Checkpoints being taken via the command line at <when> and at subsequent 1763410Shsul@eecs.umich.edu ## periods of <period>. Checkpoint instructions received from the benchmark running 1773410Shsul@eecs.umich.edu ## are ignored and skipped in favor of command line checkpoint instructions. 1783395Shsul@eecs.umich.edu if options.take_checkpoints: 1793395Shsul@eecs.umich.edu [when, period] = options.take_checkpoints.split(",", 1) 1803395Shsul@eecs.umich.edu when = int(when) 1813395Shsul@eecs.umich.edu period = int(period) 1823395Shsul@eecs.umich.edu 1833395Shsul@eecs.umich.edu exit_event = m5.simulate(when) 1843395Shsul@eecs.umich.edu while exit_event.getCause() == "checkpoint": 1853395Shsul@eecs.umich.edu exit_event = m5.simulate(when - m5.curTick()) 1863395Shsul@eecs.umich.edu 1873395Shsul@eecs.umich.edu if exit_event.getCause() == "simulate() limit reached": 1883509Shsul@eecs.umich.edu m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) 1893395Shsul@eecs.umich.edu num_checkpoints += 1 1903395Shsul@eecs.umich.edu 1913395Shsul@eecs.umich.edu sim_ticks = when 1923395Shsul@eecs.umich.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 1933395Shsul@eecs.umich.edu while num_checkpoints < max_checkpoints: 1943511Shsul@eecs.umich.edu if (sim_ticks + period) > maxtick: 1953395Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick - sim_ticks) 1963395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 1973395Shsul@eecs.umich.edu break 1983395Shsul@eecs.umich.edu else: 1993395Shsul@eecs.umich.edu exit_event = m5.simulate(period) 2003395Shsul@eecs.umich.edu sim_ticks += period 2013395Shsul@eecs.umich.edu while exit_event.getCause() == "checkpoint": 2023395Shsul@eecs.umich.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 2033395Shsul@eecs.umich.edu if exit_event.getCause() == "simulate() limit reached": 2043509Shsul@eecs.umich.edu m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) 2053395Shsul@eecs.umich.edu num_checkpoints += 1 2063395Shsul@eecs.umich.edu 2073395Shsul@eecs.umich.edu else: #no checkpoints being taken via this script 2083395Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick) 2093395Shsul@eecs.umich.edu 2103395Shsul@eecs.umich.edu while exit_event.getCause() == "checkpoint": 2113509Shsul@eecs.umich.edu m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) 2123395Shsul@eecs.umich.edu num_checkpoints += 1 2133395Shsul@eecs.umich.edu if num_checkpoints == max_checkpoints: 2143395Shsul@eecs.umich.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 2153395Shsul@eecs.umich.edu break 2163395Shsul@eecs.umich.edu 2173511Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2183395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 2193395Shsul@eecs.umich.edu 2203395Shsul@eecs.umich.edu if exit_cause == '': 2213395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 2223395Shsul@eecs.umich.edu print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause 2233395Shsul@eecs.umich.edu 224