Simulation.py revision 13731
19793Sakash.bagdia@arm.com# Copyright (c) 2012-2013 ARM Limited 29518SAndreas.Sandberg@ARM.com# All rights reserved 311320Ssteve.reinhardt@amd.com# 49518SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59518SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69518SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79518SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89518SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99518SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109518SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119518SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129518SAndreas.Sandberg@ARM.com# 135347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 147534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 153395Shsul@eecs.umich.edu# All rights reserved. 163395Shsul@eecs.umich.edu# 173395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 183395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 193395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 203395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 213395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 223395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 233395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 243395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 253395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 263395Shsul@eecs.umich.edu# this software without specific prior written permission. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393395Shsul@eecs.umich.edu# 403395Shsul@eecs.umich.edu# Authors: Lisa Hsu 413395Shsul@eecs.umich.edu 4212564Sgabeblack@google.comfrom __future__ import print_function 4312564Sgabeblack@google.com 449457Svilanova@ac.upc.eduimport sys 453395Shsul@eecs.umich.edufrom os import getcwd 463509Shsul@eecs.umich.edufrom os.path import join as joinpath 476654Snate@binkert.org 4811688Sandreas.hansson@arm.comfrom common import CpuConfig 4913432Spau.cabre@metempsy.comfrom common import BPConfig 5011688Sandreas.hansson@arm.comfrom common import MemConfig 519520SAndreas.Sandberg@ARM.com 523395Shsul@eecs.umich.eduimport m5 536654Snate@binkert.orgfrom m5.defines import buildEnv 543395Shsul@eecs.umich.edufrom m5.objects import * 556654Snate@binkert.orgfrom m5.util import * 566654Snate@binkert.org 576654Snate@binkert.orgaddToPath('../common') 583395Shsul@eecs.umich.edu 599139Snilay@cs.wisc.edudef getCPUClass(cpu_type): 609520SAndreas.Sandberg@ARM.com """Returns the required cpu class and the mode of operation.""" 619520SAndreas.Sandberg@ARM.com cls = CpuConfig.get(cpu_type) 629520SAndreas.Sandberg@ARM.com return cls, cls.memory_mode() 639139Snilay@cs.wisc.edu 643481Shsul@eecs.umich.edudef setCPUClass(options): 659139Snilay@cs.wisc.edu """Returns two cpu classes and the initial mode of operation. 663481Shsul@eecs.umich.edu 679139Snilay@cs.wisc.edu Restoring from a checkpoint or fast forwarding through a benchmark 689139Snilay@cs.wisc.edu can be done using one type of cpu, and then the actual 699139Snilay@cs.wisc.edu simulation can be carried out using another type. This function 709139Snilay@cs.wisc.edu returns these two types of cpus and the initial mode of operation 719139Snilay@cs.wisc.edu depending on the options provided. 729139Snilay@cs.wisc.edu """ 739139Snilay@cs.wisc.edu 749139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.cpu_type) 753481Shsul@eecs.umich.edu CPUClass = None 769518SAndreas.Sandberg@ARM.com if TmpClass.require_caches() and \ 779518SAndreas.Sandberg@ARM.com not options.caches and not options.ruby: 789518SAndreas.Sandberg@ARM.com fatal("%s must be used with caches" % options.cpu_type) 793481Shsul@eecs.umich.edu 809139Snilay@cs.wisc.edu if options.checkpoint_restore != None: 819139Snilay@cs.wisc.edu if options.restore_with_cpu != options.cpu_type: 823481Shsul@eecs.umich.edu CPUClass = TmpClass 839139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu) 849139Snilay@cs.wisc.edu elif options.fast_forward: 859139Snilay@cs.wisc.edu CPUClass = TmpClass 869139Snilay@cs.wisc.edu TmpClass = AtomicSimpleCPU 879139Snilay@cs.wisc.edu test_mem_mode = 'atomic' 883481Shsul@eecs.umich.edu 8912395Sswapnilster@gmail.com # Ruby only supports atomic accesses in noncaching mode 9012395Sswapnilster@gmail.com if test_mem_mode == 'atomic' and options.ruby: 9112395Sswapnilster@gmail.com warn("Memory mode will be changed to atomic_noncaching") 9212395Sswapnilster@gmail.com test_mem_mode = 'atomic_noncaching' 9312395Sswapnilster@gmail.com 943481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 953481Shsul@eecs.umich.edu 969665Sandreas.hansson@arm.comdef setMemClass(options): 979665Sandreas.hansson@arm.com """Returns a memory controller class.""" 989665Sandreas.hansson@arm.com 999665Sandreas.hansson@arm.com return MemConfig.get(options.mem_type) 1009665Sandreas.hansson@arm.com 1018919Snilay@cs.wisc.edudef setWorkCountOptions(system, options): 1028919Snilay@cs.wisc.edu if options.work_item_id != None: 1038919Snilay@cs.wisc.edu system.work_item_id = options.work_item_id 10410159Sgedare@rtems.org if options.num_work_ids != None: 10510159Sgedare@rtems.org system.num_work_ids = options.num_work_ids 1068919Snilay@cs.wisc.edu if options.work_begin_cpu_id_exit != None: 1078919Snilay@cs.wisc.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 1088919Snilay@cs.wisc.edu if options.work_end_exit_count != None: 1098919Snilay@cs.wisc.edu system.work_end_exit_count = options.work_end_exit_count 1108919Snilay@cs.wisc.edu if options.work_end_checkpoint_count != None: 1118919Snilay@cs.wisc.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 1128919Snilay@cs.wisc.edu if options.work_begin_exit_count != None: 1138919Snilay@cs.wisc.edu system.work_begin_exit_count = options.work_begin_exit_count 1148919Snilay@cs.wisc.edu if options.work_begin_checkpoint_count != None: 1158919Snilay@cs.wisc.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 1168919Snilay@cs.wisc.edu if options.work_cpus_checkpoint_count != None: 1178919Snilay@cs.wisc.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 1183481Shsul@eecs.umich.edu 1199816Sjthestness@gmail.comdef findCptDir(options, cptdir, testsys): 1209140Snilay@cs.wisc.edu """Figures out the directory from which the checkpointed state is read. 1219140Snilay@cs.wisc.edu 1229140Snilay@cs.wisc.edu There are two different ways in which the directories holding checkpoints 1239140Snilay@cs.wisc.edu can be named -- 1249140Snilay@cs.wisc.edu 1. cpt.<benchmark name>.<instruction count when the checkpoint was taken> 1259140Snilay@cs.wisc.edu 2. cpt.<some number, usually the tick value when the checkpoint was taken> 1269140Snilay@cs.wisc.edu 1279140Snilay@cs.wisc.edu This function parses through the options to figure out which one of the 1289140Snilay@cs.wisc.edu above should be used for selecting the checkpoint, and then figures out 1299140Snilay@cs.wisc.edu the appropriate directory. 1309140Snilay@cs.wisc.edu """ 1319140Snilay@cs.wisc.edu 1329140Snilay@cs.wisc.edu from os.path import isdir, exists 1339140Snilay@cs.wisc.edu from os import listdir 1349140Snilay@cs.wisc.edu import re 1359140Snilay@cs.wisc.edu 1369140Snilay@cs.wisc.edu if not isdir(cptdir): 1379140Snilay@cs.wisc.edu fatal("checkpoint dir %s does not exist!", cptdir) 1389140Snilay@cs.wisc.edu 1399867Sjthestness@gmail.com cpt_starttick = 0 1409140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1419140Snilay@cs.wisc.edu inst = options.checkpoint_restore 1429140Snilay@cs.wisc.edu if options.simpoint: 1439140Snilay@cs.wisc.edu # assume workload 0 has the simpoint 1449140Snilay@cs.wisc.edu if testsys.cpu[0].workload[0].simpoint == 0: 1459140Snilay@cs.wisc.edu fatal('Unable to find simpoint') 1469140Snilay@cs.wisc.edu inst += int(testsys.cpu[0].workload[0].simpoint) 1479140Snilay@cs.wisc.edu 1489140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) 1499140Snilay@cs.wisc.edu if not exists(checkpoint_dir): 1509140Snilay@cs.wisc.edu fatal("Unable to find checkpoint directory %s", checkpoint_dir) 15110608Sdam.sunwoo@arm.com 15210608Sdam.sunwoo@arm.com elif options.restore_simpoint_checkpoint: 15310608Sdam.sunwoo@arm.com # Restore from SimPoint checkpoints 15410608Sdam.sunwoo@arm.com # Assumes that the checkpoint dir names are formatted as follows: 15510608Sdam.sunwoo@arm.com dirs = listdir(cptdir) 15610608Sdam.sunwoo@arm.com expr = re.compile('cpt\.simpoint_(\d+)_inst_(\d+)' + 15710608Sdam.sunwoo@arm.com '_weight_([\d\.e\-]+)_interval_(\d+)_warmup_(\d+)') 15810608Sdam.sunwoo@arm.com cpts = [] 15910608Sdam.sunwoo@arm.com for dir in dirs: 16010608Sdam.sunwoo@arm.com match = expr.match(dir) 16110608Sdam.sunwoo@arm.com if match: 16210608Sdam.sunwoo@arm.com cpts.append(dir) 16310608Sdam.sunwoo@arm.com cpts.sort() 16410608Sdam.sunwoo@arm.com 16510608Sdam.sunwoo@arm.com cpt_num = options.checkpoint_restore 16610608Sdam.sunwoo@arm.com if cpt_num > len(cpts): 16710608Sdam.sunwoo@arm.com fatal('Checkpoint %d not found', cpt_num) 16810608Sdam.sunwoo@arm.com checkpoint_dir = joinpath(cptdir, cpts[cpt_num - 1]) 16910608Sdam.sunwoo@arm.com match = expr.match(cpts[cpt_num - 1]) 17010608Sdam.sunwoo@arm.com if match: 17110608Sdam.sunwoo@arm.com index = int(match.group(1)) 17210608Sdam.sunwoo@arm.com start_inst = int(match.group(2)) 17310608Sdam.sunwoo@arm.com weight_inst = float(match.group(3)) 17410608Sdam.sunwoo@arm.com interval_length = int(match.group(4)) 17510608Sdam.sunwoo@arm.com warmup_length = int(match.group(5)) 17612564Sgabeblack@google.com print("Resuming from", checkpoint_dir) 17710608Sdam.sunwoo@arm.com simpoint_start_insts = [] 17810608Sdam.sunwoo@arm.com simpoint_start_insts.append(warmup_length) 17910608Sdam.sunwoo@arm.com simpoint_start_insts.append(warmup_length + interval_length) 18010608Sdam.sunwoo@arm.com testsys.cpu[0].simpoint_start_insts = simpoint_start_insts 18110608Sdam.sunwoo@arm.com if testsys.switch_cpus != None: 18210608Sdam.sunwoo@arm.com testsys.switch_cpus[0].simpoint_start_insts = simpoint_start_insts 18310608Sdam.sunwoo@arm.com 18412564Sgabeblack@google.com print("Resuming from SimPoint", end=' ') 18512564Sgabeblack@google.com print("#%d, start_inst:%d, weight:%f, interval:%d, warmup:%d" % 18612564Sgabeblack@google.com (index, start_inst, weight_inst, interval_length, warmup_length)) 18710608Sdam.sunwoo@arm.com 1889140Snilay@cs.wisc.edu else: 1899140Snilay@cs.wisc.edu dirs = listdir(cptdir) 19010608Sdam.sunwoo@arm.com expr = re.compile('cpt\.([0-9]+)') 1919140Snilay@cs.wisc.edu cpts = [] 1929140Snilay@cs.wisc.edu for dir in dirs: 1939140Snilay@cs.wisc.edu match = expr.match(dir) 1949140Snilay@cs.wisc.edu if match: 1959140Snilay@cs.wisc.edu cpts.append(match.group(1)) 1969140Snilay@cs.wisc.edu 1979140Snilay@cs.wisc.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 1989140Snilay@cs.wisc.edu 1999140Snilay@cs.wisc.edu cpt_num = options.checkpoint_restore 2009140Snilay@cs.wisc.edu if cpt_num > len(cpts): 2019140Snilay@cs.wisc.edu fatal('Checkpoint %d not found', cpt_num) 2029140Snilay@cs.wisc.edu 2039816Sjthestness@gmail.com cpt_starttick = int(cpts[cpt_num - 1]) 2049140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 2059140Snilay@cs.wisc.edu 2069816Sjthestness@gmail.com return cpt_starttick, checkpoint_dir 2079140Snilay@cs.wisc.edu 2089215Sandreas.hansson@arm.comdef scriptCheckpoints(options, maxtick, cptdir): 2099140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 2109140Snilay@cs.wisc.edu checkpoint_inst = int(options.take_checkpoints) 2119140Snilay@cs.wisc.edu 2129140Snilay@cs.wisc.edu # maintain correct offset if we restored from some instruction 2139140Snilay@cs.wisc.edu if options.checkpoint_restore != None: 2149140Snilay@cs.wisc.edu checkpoint_inst += options.checkpoint_restore 2159140Snilay@cs.wisc.edu 21612564Sgabeblack@google.com print("Creating checkpoint at inst:%d" % (checkpoint_inst)) 2179140Snilay@cs.wisc.edu exit_event = m5.simulate() 2189140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 21912564Sgabeblack@google.com print("exit cause = %s" % exit_cause) 2209140Snilay@cs.wisc.edu 2219140Snilay@cs.wisc.edu # skip checkpoint instructions should they exist 2229140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2239140Snilay@cs.wisc.edu exit_event = m5.simulate() 2249140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2259140Snilay@cs.wisc.edu 2269140Snilay@cs.wisc.edu if exit_cause == "a thread reached the max instruction count": 2279140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 2289140Snilay@cs.wisc.edu (options.bench, checkpoint_inst))) 22912564Sgabeblack@google.com print("Checkpoint written.") 2309140Snilay@cs.wisc.edu 2319140Snilay@cs.wisc.edu else: 2329140Snilay@cs.wisc.edu when, period = options.take_checkpoints.split(",", 1) 2339140Snilay@cs.wisc.edu when = int(when) 2349140Snilay@cs.wisc.edu period = int(period) 2359156Sandreas.hansson@arm.com num_checkpoints = 0 2369140Snilay@cs.wisc.edu 2379634Sjthestness@gmail.com exit_event = m5.simulate(when - m5.curTick()) 2389140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2399140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2409140Snilay@cs.wisc.edu exit_event = m5.simulate(when - m5.curTick()) 2419140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2429140Snilay@cs.wisc.edu 2439140Snilay@cs.wisc.edu if exit_cause == "simulate() limit reached": 2449140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2459140Snilay@cs.wisc.edu num_checkpoints += 1 2469140Snilay@cs.wisc.edu 2479140Snilay@cs.wisc.edu sim_ticks = when 2489140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2499140Snilay@cs.wisc.edu 2509140Snilay@cs.wisc.edu while num_checkpoints < max_checkpoints and \ 2519140Snilay@cs.wisc.edu exit_cause == "simulate() limit reached": 2529140Snilay@cs.wisc.edu if (sim_ticks + period) > maxtick: 2539140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - sim_ticks) 2549140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2559140Snilay@cs.wisc.edu break 2569140Snilay@cs.wisc.edu else: 2579140Snilay@cs.wisc.edu exit_event = m5.simulate(period) 2589140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2599140Snilay@cs.wisc.edu sim_ticks += period 2609140Snilay@cs.wisc.edu while exit_event.getCause() == "checkpoint": 2619140Snilay@cs.wisc.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 2629140Snilay@cs.wisc.edu if exit_event.getCause() == "simulate() limit reached": 2639140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2649140Snilay@cs.wisc.edu num_checkpoints += 1 2659140Snilay@cs.wisc.edu 2669606Snilay@cs.wisc.edu return exit_event 2679140Snilay@cs.wisc.edu 2689140Snilay@cs.wisc.edudef benchCheckpoints(options, maxtick, cptdir): 2699634Sjthestness@gmail.com exit_event = m5.simulate(maxtick - m5.curTick()) 2709140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2719140Snilay@cs.wisc.edu 2729140Snilay@cs.wisc.edu num_checkpoints = 0 2739140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2749140Snilay@cs.wisc.edu 2759140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2769140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2779140Snilay@cs.wisc.edu num_checkpoints += 1 2789140Snilay@cs.wisc.edu if num_checkpoints == max_checkpoints: 2799140Snilay@cs.wisc.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 2809140Snilay@cs.wisc.edu break 2819140Snilay@cs.wisc.edu 2829140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2839140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2849140Snilay@cs.wisc.edu 2859460Ssaidi@eecs.umich.edu return exit_event 2869140Snilay@cs.wisc.edu 28710608Sdam.sunwoo@arm.com# Set up environment for taking SimPoint checkpoints 28810608Sdam.sunwoo@arm.com# Expecting SimPoint files generated by SimPoint 3.2 28910608Sdam.sunwoo@arm.comdef parseSimpointAnalysisFile(options, testsys): 29010608Sdam.sunwoo@arm.com import re 29110608Sdam.sunwoo@arm.com 29210608Sdam.sunwoo@arm.com simpoint_filename, weight_filename, interval_length, warmup_length = \ 29310608Sdam.sunwoo@arm.com options.take_simpoint_checkpoints.split(",", 3) 29412564Sgabeblack@google.com print("simpoint analysis file:", simpoint_filename) 29512564Sgabeblack@google.com print("simpoint weight file:", weight_filename) 29612564Sgabeblack@google.com print("interval length:", interval_length) 29712564Sgabeblack@google.com print("warmup length:", warmup_length) 29810608Sdam.sunwoo@arm.com 29910608Sdam.sunwoo@arm.com interval_length = int(interval_length) 30010608Sdam.sunwoo@arm.com warmup_length = int(warmup_length) 30110608Sdam.sunwoo@arm.com 30210608Sdam.sunwoo@arm.com # Simpoint analysis output starts interval counts with 0. 30310608Sdam.sunwoo@arm.com simpoints = [] 30410608Sdam.sunwoo@arm.com simpoint_start_insts = [] 30510608Sdam.sunwoo@arm.com 30610608Sdam.sunwoo@arm.com # Read in SimPoint analysis files 30710608Sdam.sunwoo@arm.com simpoint_file = open(simpoint_filename) 30810608Sdam.sunwoo@arm.com weight_file = open(weight_filename) 30910608Sdam.sunwoo@arm.com while True: 31010608Sdam.sunwoo@arm.com line = simpoint_file.readline() 31110608Sdam.sunwoo@arm.com if not line: 31210608Sdam.sunwoo@arm.com break 31310608Sdam.sunwoo@arm.com m = re.match("(\d+)\s+(\d+)", line) 31410608Sdam.sunwoo@arm.com if m: 31510608Sdam.sunwoo@arm.com interval = int(m.group(1)) 31610608Sdam.sunwoo@arm.com else: 31710608Sdam.sunwoo@arm.com fatal('unrecognized line in simpoint file!') 31810608Sdam.sunwoo@arm.com 31910608Sdam.sunwoo@arm.com line = weight_file.readline() 32010608Sdam.sunwoo@arm.com if not line: 32110608Sdam.sunwoo@arm.com fatal('not enough lines in simpoint weight file!') 32210608Sdam.sunwoo@arm.com m = re.match("([0-9\.e\-]+)\s+(\d+)", line) 32310608Sdam.sunwoo@arm.com if m: 32410608Sdam.sunwoo@arm.com weight = float(m.group(1)) 32510608Sdam.sunwoo@arm.com else: 32610608Sdam.sunwoo@arm.com fatal('unrecognized line in simpoint weight file!') 32710608Sdam.sunwoo@arm.com 32810608Sdam.sunwoo@arm.com if (interval * interval_length - warmup_length > 0): 32910608Sdam.sunwoo@arm.com starting_inst_count = \ 33010608Sdam.sunwoo@arm.com interval * interval_length - warmup_length 33110608Sdam.sunwoo@arm.com actual_warmup_length = warmup_length 33210608Sdam.sunwoo@arm.com else: 33310608Sdam.sunwoo@arm.com # Not enough room for proper warmup 33410608Sdam.sunwoo@arm.com # Just starting from the beginning 33510608Sdam.sunwoo@arm.com starting_inst_count = 0 33610608Sdam.sunwoo@arm.com actual_warmup_length = interval * interval_length 33710608Sdam.sunwoo@arm.com 33810608Sdam.sunwoo@arm.com simpoints.append((interval, weight, starting_inst_count, 33910608Sdam.sunwoo@arm.com actual_warmup_length)) 34010608Sdam.sunwoo@arm.com 34110608Sdam.sunwoo@arm.com # Sort SimPoints by starting inst count 34210608Sdam.sunwoo@arm.com simpoints.sort(key=lambda obj: obj[2]) 34310608Sdam.sunwoo@arm.com for s in simpoints: 34410608Sdam.sunwoo@arm.com interval, weight, starting_inst_count, actual_warmup_length = s 34512564Sgabeblack@google.com print(str(interval), str(weight), starting_inst_count, 34612564Sgabeblack@google.com actual_warmup_length) 34710608Sdam.sunwoo@arm.com simpoint_start_insts.append(starting_inst_count) 34810608Sdam.sunwoo@arm.com 34912564Sgabeblack@google.com print("Total # of simpoints:", len(simpoints)) 35010608Sdam.sunwoo@arm.com testsys.cpu[0].simpoint_start_insts = simpoint_start_insts 35110608Sdam.sunwoo@arm.com 35210608Sdam.sunwoo@arm.com return (simpoints, interval_length) 35310608Sdam.sunwoo@arm.com 35410608Sdam.sunwoo@arm.comdef takeSimpointCheckpoints(simpoints, interval_length, cptdir): 35510608Sdam.sunwoo@arm.com num_checkpoints = 0 35610608Sdam.sunwoo@arm.com index = 0 35710608Sdam.sunwoo@arm.com last_chkpnt_inst_count = -1 35810608Sdam.sunwoo@arm.com for simpoint in simpoints: 35910608Sdam.sunwoo@arm.com interval, weight, starting_inst_count, actual_warmup_length = simpoint 36010608Sdam.sunwoo@arm.com if starting_inst_count == last_chkpnt_inst_count: 36110608Sdam.sunwoo@arm.com # checkpoint starting point same as last time 36210608Sdam.sunwoo@arm.com # (when warmup period longer than starting point) 36310608Sdam.sunwoo@arm.com exit_cause = "simpoint starting point found" 36410608Sdam.sunwoo@arm.com code = 0 36510608Sdam.sunwoo@arm.com else: 36610608Sdam.sunwoo@arm.com exit_event = m5.simulate() 36710608Sdam.sunwoo@arm.com 36810608Sdam.sunwoo@arm.com # skip checkpoint instructions should they exist 36910608Sdam.sunwoo@arm.com while exit_event.getCause() == "checkpoint": 37012564Sgabeblack@google.com print("Found 'checkpoint' exit event...ignoring...") 37110608Sdam.sunwoo@arm.com exit_event = m5.simulate() 37210608Sdam.sunwoo@arm.com 37310608Sdam.sunwoo@arm.com exit_cause = exit_event.getCause() 37410608Sdam.sunwoo@arm.com code = exit_event.getCode() 37510608Sdam.sunwoo@arm.com 37610608Sdam.sunwoo@arm.com if exit_cause == "simpoint starting point found": 37710608Sdam.sunwoo@arm.com m5.checkpoint(joinpath(cptdir, 37810608Sdam.sunwoo@arm.com "cpt.simpoint_%02d_inst_%d_weight_%f_interval_%d_warmup_%d" 37910608Sdam.sunwoo@arm.com % (index, starting_inst_count, weight, interval_length, 38010608Sdam.sunwoo@arm.com actual_warmup_length))) 38112564Sgabeblack@google.com print("Checkpoint #%d written. start inst:%d weight:%f" % 38212564Sgabeblack@google.com (num_checkpoints, starting_inst_count, weight)) 38310608Sdam.sunwoo@arm.com num_checkpoints += 1 38410608Sdam.sunwoo@arm.com last_chkpnt_inst_count = starting_inst_count 38510608Sdam.sunwoo@arm.com else: 38610608Sdam.sunwoo@arm.com break 38710608Sdam.sunwoo@arm.com index += 1 38810608Sdam.sunwoo@arm.com 38912564Sgabeblack@google.com print('Exiting @ tick %i because %s' % (m5.curTick(), exit_cause)) 39012564Sgabeblack@google.com print("%d checkpoints taken" % num_checkpoints) 39110608Sdam.sunwoo@arm.com sys.exit(code) 39210608Sdam.sunwoo@arm.com 39310608Sdam.sunwoo@arm.comdef restoreSimpointCheckpoint(): 39410608Sdam.sunwoo@arm.com exit_event = m5.simulate() 39510608Sdam.sunwoo@arm.com exit_cause = exit_event.getCause() 39610608Sdam.sunwoo@arm.com 39710608Sdam.sunwoo@arm.com if exit_cause == "simpoint starting point found": 39812564Sgabeblack@google.com print("Warmed up! Dumping and resetting stats!") 39910608Sdam.sunwoo@arm.com m5.stats.dump() 40010608Sdam.sunwoo@arm.com m5.stats.reset() 40110608Sdam.sunwoo@arm.com 40210608Sdam.sunwoo@arm.com exit_event = m5.simulate() 40310608Sdam.sunwoo@arm.com exit_cause = exit_event.getCause() 40410608Sdam.sunwoo@arm.com 40510608Sdam.sunwoo@arm.com if exit_cause == "simpoint starting point found": 40612564Sgabeblack@google.com print("Done running SimPoint!") 40710608Sdam.sunwoo@arm.com sys.exit(exit_event.getCode()) 40810608Sdam.sunwoo@arm.com 40912564Sgabeblack@google.com print('Exiting @ tick %i because %s' % (m5.curTick(), exit_cause)) 41010608Sdam.sunwoo@arm.com sys.exit(exit_event.getCode()) 41110608Sdam.sunwoo@arm.com 4129151Satgutier@umich.edudef repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, switch_freq): 41312564Sgabeblack@google.com print("starting switch loop") 4149151Satgutier@umich.edu while True: 4159151Satgutier@umich.edu exit_event = m5.simulate(switch_freq) 4169151Satgutier@umich.edu exit_cause = exit_event.getCause() 4179151Satgutier@umich.edu 4189151Satgutier@umich.edu if exit_cause != "simulate() limit reached": 4199460Ssaidi@eecs.umich.edu return exit_event 4209151Satgutier@umich.edu 4219521SAndreas.Sandberg@ARM.com m5.switchCpus(testsys, repeat_switch_cpu_list) 4229151Satgutier@umich.edu 4239151Satgutier@umich.edu tmp_cpu_list = [] 4249151Satgutier@umich.edu for old_cpu, new_cpu in repeat_switch_cpu_list: 4259151Satgutier@umich.edu tmp_cpu_list.append((new_cpu, old_cpu)) 4269151Satgutier@umich.edu repeat_switch_cpu_list = tmp_cpu_list 4279151Satgutier@umich.edu 4289151Satgutier@umich.edu if (maxtick - m5.curTick()) <= switch_freq: 4299151Satgutier@umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 4309460Ssaidi@eecs.umich.edu return exit_event 4319151Satgutier@umich.edu 4323481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 4333395Shsul@eecs.umich.edu if options.checkpoint_dir: 4343395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 4355211Ssaidi@eecs.umich.edu elif m5.options.outdir: 4365211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 4373395Shsul@eecs.umich.edu else: 4383395Shsul@eecs.umich.edu cptdir = getcwd() 4393395Shsul@eecs.umich.edu 4405370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 4416654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 4425370Ssaidi@eecs.umich.edu 4435371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 4446654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 4455370Ssaidi@eecs.umich.edu 4469151Satgutier@umich.edu if options.standard_switch and options.repeat_switch: 4479151Satgutier@umich.edu fatal("Can't specify both --standard-switch and --repeat-switch") 4489151Satgutier@umich.edu 4499151Satgutier@umich.edu if options.repeat_switch and options.take_checkpoints: 4509151Satgutier@umich.edu fatal("Can't specify both --repeat-switch and --take-checkpoints") 4519151Satgutier@umich.edu 4523395Shsul@eecs.umich.edu np = options.num_cpus 4533481Shsul@eecs.umich.edu switch_cpus = None 4543481Shsul@eecs.umich.edu 4558318Sksewell@umich.edu if options.prog_interval: 45613731Sandreas.sandberg@arm.com for i in range(np): 4578311Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_interval 4586144Sksewell@umich.edu 4596641Sksewell@umich.edu if options.maxinsts: 46013731Sandreas.sandberg@arm.com for i in range(np): 4616641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 4626641Sksewell@umich.edu 4633481Shsul@eecs.umich.edu if cpu_class: 4649433SAndreas.Sandberg@ARM.com switch_cpus = [cpu_class(switched_out=True, cpu_id=(i)) 46513731Sandreas.sandberg@arm.com for i in range(np)] 4663481Shsul@eecs.umich.edu 46713731Sandreas.sandberg@arm.com for i in range(np): 4685361Srstrong@cs.ucsd.edu if options.fast_forward: 4695369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 47011251Sradhika.jagtap@ARM.com switch_cpus[i].system = testsys 4718803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 4729793Sakash.bagdia@arm.com switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain 47311251Sradhika.jagtap@ARM.com switch_cpus[i].progress_interval = \ 47411251Sradhika.jagtap@ARM.com testsys.cpu[i].progress_interval 47512374Saustinharris@utexas.edu switch_cpus[i].isa = testsys.cpu[i].isa 4765369Ssaidi@eecs.umich.edu # simulation period 4778311Sksewell@umich.edu if options.maxinsts: 4788311Sksewell@umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 4798887Sgeoffrey.blake@arm.com # Add checker cpu if selected 4808887Sgeoffrey.blake@arm.com if options.checker: 4818887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 48213432Spau.cabre@metempsy.com if options.bp_type: 48313432Spau.cabre@metempsy.com bpClass = BPConfig.get(options.bp_type) 48413432Spau.cabre@metempsy.com switch_cpus[i].branchPred = bpClass() 4853481Shsul@eecs.umich.edu 48611251Sradhika.jagtap@ARM.com # If elastic tracing is enabled attach the elastic trace probe 48711251Sradhika.jagtap@ARM.com # to the switch CPUs 48811251Sradhika.jagtap@ARM.com if options.elastic_trace_en: 48911251Sradhika.jagtap@ARM.com CpuConfig.config_etrace(cpu_class, switch_cpus, options) 49011251Sradhika.jagtap@ARM.com 4915311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 49213731Sandreas.sandberg@arm.com switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in range(np)] 4933395Shsul@eecs.umich.edu 4949151Satgutier@umich.edu if options.repeat_switch: 4959518SAndreas.Sandberg@ARM.com switch_class = getCPUClass(options.cpu_type)[0] 4969518SAndreas.Sandberg@ARM.com if switch_class.require_caches() and \ 4979518SAndreas.Sandberg@ARM.com not options.caches: 49812564Sgabeblack@google.com print("%s: Must be used with caches" % str(switch_class)) 4999518SAndreas.Sandberg@ARM.com sys.exit(1) 5009518SAndreas.Sandberg@ARM.com if not switch_class.support_take_over(): 50112564Sgabeblack@google.com print("%s: CPU switching not supported" % str(switch_class)) 5029518SAndreas.Sandberg@ARM.com sys.exit(1) 5039151Satgutier@umich.edu 5049518SAndreas.Sandberg@ARM.com repeat_switch_cpus = [switch_class(switched_out=True, \ 50513731Sandreas.sandberg@arm.com cpu_id=(i)) for i in range(np)] 5069151Satgutier@umich.edu 50713731Sandreas.sandberg@arm.com for i in range(np): 5089151Satgutier@umich.edu repeat_switch_cpus[i].system = testsys 5099151Satgutier@umich.edu repeat_switch_cpus[i].workload = testsys.cpu[i].workload 5109793Sakash.bagdia@arm.com repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain 51112374Saustinharris@utexas.edu repeat_switch_cpus[i].isa = testsys.cpu[i].isa 5129151Satgutier@umich.edu 5139151Satgutier@umich.edu if options.maxinsts: 5149151Satgutier@umich.edu repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts 5159151Satgutier@umich.edu 5169151Satgutier@umich.edu if options.checker: 5179151Satgutier@umich.edu repeat_switch_cpus[i].addCheckerCpu() 5189151Satgutier@umich.edu 5199151Satgutier@umich.edu testsys.repeat_switch_cpus = repeat_switch_cpus 5209151Satgutier@umich.edu 5219151Satgutier@umich.edu if cpu_class: 5229151Satgutier@umich.edu repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) 52313731Sandreas.sandberg@arm.com for i in range(np)] 5249151Satgutier@umich.edu else: 5259151Satgutier@umich.edu repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) 52613731Sandreas.sandberg@arm.com for i in range(np)] 5279151Satgutier@umich.edu 5283395Shsul@eecs.umich.edu if options.standard_switch: 5299433SAndreas.Sandberg@ARM.com switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i)) 53013731Sandreas.sandberg@arm.com for i in range(np)] 5319433SAndreas.Sandberg@ARM.com switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i)) 53213731Sandreas.sandberg@arm.com for i in range(np)] 5333478Shsul@eecs.umich.edu 53413731Sandreas.sandberg@arm.com for i in range(np): 5353395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 5363478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 5378803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 5388803Sgblack@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 5399793Sakash.bagdia@arm.com switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain 5409793Sakash.bagdia@arm.com switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain 54112374Saustinharris@utexas.edu switch_cpus[i].isa = testsys.cpu[i].isa 54212374Saustinharris@utexas.edu switch_cpus_1[i].isa = testsys.cpu[i].isa 5433480Shsul@eecs.umich.edu 5445361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 5455369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 5465361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 5475361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 5485361Srstrong@cs.ucsd.edu elif options.fast_forward: 5495369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 5505361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 5515361Srstrong@cs.ucsd.edu elif options.simpoint: 5525378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 5536654Snate@binkert.org fatal('simpoint not found') 5545361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 5555361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 5565361Srstrong@cs.ucsd.edu # No distance specified, just switch 5575361Srstrong@cs.ucsd.edu else: 5585361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 5595361Srstrong@cs.ucsd.edu 5605361Srstrong@cs.ucsd.edu # warmup period 5615361Srstrong@cs.ucsd.edu if options.warmup_insts: 5625361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 5635361Srstrong@cs.ucsd.edu 5645361Srstrong@cs.ucsd.edu # simulation period 5658311Sksewell@umich.edu if options.maxinsts: 5668311Sksewell@umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 5675353Svilas.sridharan@gmail.com 5688887Sgeoffrey.blake@arm.com # attach the checker cpu if selected 5698887Sgeoffrey.blake@arm.com if options.checker: 5708887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 5718887Sgeoffrey.blake@arm.com switch_cpus_1[i].addCheckerCpu() 5728887Sgeoffrey.blake@arm.com 5738211Satgutier@umich.edu testsys.switch_cpus = switch_cpus 5748211Satgutier@umich.edu testsys.switch_cpus_1 = switch_cpus_1 57513731Sandreas.sandberg@arm.com switch_cpu_list = [ 57613731Sandreas.sandberg@arm.com (testsys.cpu[i], switch_cpus[i]) for i in range(np) 57713731Sandreas.sandberg@arm.com ] 57813731Sandreas.sandberg@arm.com switch_cpu_list1 = [ 57913731Sandreas.sandberg@arm.com (switch_cpus[i], switch_cpus_1[i]) for i in range(np) 58013731Sandreas.sandberg@arm.com ] 5813395Shsul@eecs.umich.edu 5825361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 5835369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 5845361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 5855361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 5865361Srstrong@cs.ucsd.edu # Set an instruction break point 5875361Srstrong@cs.ucsd.edu if options.simpoint: 58813731Sandreas.sandberg@arm.com for i in range(np): 5895378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 5906654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 5915369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 5925361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 5935361Srstrong@cs.ucsd.edu # used for output below 5945361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 5955361Srstrong@cs.ucsd.edu else: 5965361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 5975361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 5985361Srstrong@cs.ucsd.edu # for the upcoming simulation 59913731Sandreas.sandberg@arm.com for i in range(np): 6005361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 6015361Srstrong@cs.ucsd.edu 60210608Sdam.sunwoo@arm.com if options.take_simpoint_checkpoints != None: 60310608Sdam.sunwoo@arm.com simpoints, interval_length = parseSimpointAnalysisFile(options, testsys) 60410608Sdam.sunwoo@arm.com 6057531Ssteve.reinhardt@amd.com checkpoint_dir = None 6069816Sjthestness@gmail.com if options.checkpoint_restore: 6079816Sjthestness@gmail.com cpt_starttick, checkpoint_dir = findCptDir(options, cptdir, testsys) 60813357Sciro.santilli@arm.com root.apply_config(options.param) 6097531Ssteve.reinhardt@amd.com m5.instantiate(checkpoint_dir) 6103395Shsul@eecs.umich.edu 61110757SCurtis.Dunham@arm.com # Initialization is complete. If we're not in control of simulation 61210757SCurtis.Dunham@arm.com # (that is, if we're a slave simulator acting as a component in another 61310757SCurtis.Dunham@arm.com # 'master' simulator) then we're done here. The other simulator will 61410757SCurtis.Dunham@arm.com # call simulate() directly. --initialize-only is used to indicate this. 61510757SCurtis.Dunham@arm.com if options.initialize_only: 61610757SCurtis.Dunham@arm.com return 61710757SCurtis.Dunham@arm.com 6189816Sjthestness@gmail.com # Handle the max tick settings now that tick frequency was resolved 6199816Sjthestness@gmail.com # during system instantiation 6209816Sjthestness@gmail.com # NOTE: the maxtick variable here is in absolute ticks, so it must 6219816Sjthestness@gmail.com # include any simulated ticks before a checkpoint 6229816Sjthestness@gmail.com explicit_maxticks = 0 6239816Sjthestness@gmail.com maxtick_from_abs = m5.MaxTick 6249816Sjthestness@gmail.com maxtick_from_rel = m5.MaxTick 6259816Sjthestness@gmail.com maxtick_from_maxtime = m5.MaxTick 6269816Sjthestness@gmail.com if options.abs_max_tick: 6279816Sjthestness@gmail.com maxtick_from_abs = options.abs_max_tick 6289816Sjthestness@gmail.com explicit_maxticks += 1 6299816Sjthestness@gmail.com if options.rel_max_tick: 6309816Sjthestness@gmail.com maxtick_from_rel = options.rel_max_tick 6319816Sjthestness@gmail.com if options.checkpoint_restore: 6329816Sjthestness@gmail.com # NOTE: this may need to be updated if checkpoints ever store 6339816Sjthestness@gmail.com # the ticks per simulated second 6349816Sjthestness@gmail.com maxtick_from_rel += cpt_starttick 6359867Sjthestness@gmail.com if options.at_instruction or options.simpoint: 6369867Sjthestness@gmail.com warn("Relative max tick specified with --at-instruction or" \ 6379867Sjthestness@gmail.com " --simpoint\n These options don't specify the " \ 6389867Sjthestness@gmail.com "checkpoint start tick, so assuming\n you mean " \ 6399867Sjthestness@gmail.com "absolute max tick") 6409816Sjthestness@gmail.com explicit_maxticks += 1 6419816Sjthestness@gmail.com if options.maxtime: 6429816Sjthestness@gmail.com maxtick_from_maxtime = m5.ticks.fromSeconds(options.maxtime) 6439816Sjthestness@gmail.com explicit_maxticks += 1 6449816Sjthestness@gmail.com if explicit_maxticks > 1: 6459816Sjthestness@gmail.com warn("Specified multiple of --abs-max-tick, --rel-max-tick, --maxtime."\ 6469816Sjthestness@gmail.com " Using least") 6479816Sjthestness@gmail.com maxtick = min([maxtick_from_abs, maxtick_from_rel, maxtick_from_maxtime]) 6489816Sjthestness@gmail.com 6499816Sjthestness@gmail.com if options.checkpoint_restore != None and maxtick < cpt_starttick: 6509816Sjthestness@gmail.com fatal("Bad maxtick (%d) specified: " \ 6519816Sjthestness@gmail.com "Checkpoint starts starts from tick: %d", maxtick, cpt_starttick) 6529816Sjthestness@gmail.com 6533481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 6545361Srstrong@cs.ucsd.edu if options.standard_switch: 65512564Sgabeblack@google.com print("Switch at instruction count:%s" % 65612564Sgabeblack@google.com str(testsys.cpu[0].max_insts_any_thread)) 6575361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 6585361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 65912564Sgabeblack@google.com print("Switch at instruction count:%s" % 66012564Sgabeblack@google.com str(testsys.cpu[0].max_insts_any_thread)) 6615361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 6625361Srstrong@cs.ucsd.edu else: 66312564Sgabeblack@google.com print("Switch at curTick count:%s" % str(10000)) 6645361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 66512564Sgabeblack@google.com print("Switched CPUS @ tick %s" % (m5.curTick())) 6663395Shsul@eecs.umich.edu 6679521SAndreas.Sandberg@ARM.com m5.switchCpus(testsys, switch_cpu_list) 6683395Shsul@eecs.umich.edu 6693481Shsul@eecs.umich.edu if options.standard_switch: 67012564Sgabeblack@google.com print("Switch at instruction count:%d" % 67112564Sgabeblack@google.com (testsys.switch_cpus[0].max_insts_any_thread)) 6725361Srstrong@cs.ucsd.edu 6735361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 6745361Srstrong@cs.ucsd.edu if options.warmup_insts: 6755361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 6765361Srstrong@cs.ucsd.edu else: 6779151Satgutier@umich.edu exit_event = m5.simulate(options.standard_switch) 67812564Sgabeblack@google.com print("Switching CPUS @ tick %s" % (m5.curTick())) 67912564Sgabeblack@google.com print("Simulation ends instruction count:%d" % 68012564Sgabeblack@google.com (testsys.switch_cpus_1[0].max_insts_any_thread)) 6819521SAndreas.Sandberg@ARM.com m5.switchCpus(testsys, switch_cpu_list1) 6823395Shsul@eecs.umich.edu 6837489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 6847489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 6857489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 6867489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 68710608Sdam.sunwoo@arm.com if (options.take_checkpoints or options.take_simpoint_checkpoints) \ 68810608Sdam.sunwoo@arm.com and options.checkpoint_restore: 68910608Sdam.sunwoo@arm.com 6907489Ssteve.reinhardt@amd.com if m5.options.outdir: 6917489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 6927489Ssteve.reinhardt@amd.com else: 6937489Ssteve.reinhardt@amd.com cptdir = getcwd() 6947489Ssteve.reinhardt@amd.com 6955369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 6969140Snilay@cs.wisc.edu # Checkpoints being taken via the command line at <when> and at 6979140Snilay@cs.wisc.edu # subsequent periods of <period>. Checkpoint instructions 6989140Snilay@cs.wisc.edu # received from the benchmark running are ignored and skipped in 6999140Snilay@cs.wisc.edu # favor of command line checkpoint instructions. 7009606Snilay@cs.wisc.edu exit_event = scriptCheckpoints(options, maxtick, cptdir) 70110608Sdam.sunwoo@arm.com 70210608Sdam.sunwoo@arm.com # Take SimPoint checkpoints 70310608Sdam.sunwoo@arm.com elif options.take_simpoint_checkpoints != None: 70410608Sdam.sunwoo@arm.com takeSimpointCheckpoints(simpoints, interval_length, cptdir) 70510608Sdam.sunwoo@arm.com 70610608Sdam.sunwoo@arm.com # Restore from SimPoint checkpoints 70710608Sdam.sunwoo@arm.com elif options.restore_simpoint_checkpoint != None: 70810608Sdam.sunwoo@arm.com restoreSimpointCheckpoint() 70910608Sdam.sunwoo@arm.com 7109140Snilay@cs.wisc.edu else: 7119151Satgutier@umich.edu if options.fast_forward: 7129151Satgutier@umich.edu m5.stats.reset() 71312564Sgabeblack@google.com print("**** REAL SIMULATION ****") 7149151Satgutier@umich.edu 7159140Snilay@cs.wisc.edu # If checkpoints are being taken, then the checkpoint instruction 7169140Snilay@cs.wisc.edu # will occur in the benchmark code it self. 7179151Satgutier@umich.edu if options.repeat_switch and maxtick > options.repeat_switch: 7189460Ssaidi@eecs.umich.edu exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, 7199151Satgutier@umich.edu maxtick, options.repeat_switch) 7209151Satgutier@umich.edu else: 7219460Ssaidi@eecs.umich.edu exit_event = benchCheckpoints(options, maxtick, cptdir) 7223395Shsul@eecs.umich.edu 72312564Sgabeblack@google.com print('Exiting @ tick %i because %s' % 72412564Sgabeblack@google.com (m5.curTick(), exit_event.getCause())) 7256776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 7267525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 7279457Svilanova@ac.upc.edu 72812880Sjason@lowepower.com if exit_event.getCode() != 0: 72912880Sjason@lowepower.com print("Simulated exit code not 0! Exit code is", exit_event.getCode()) 730