Simulation.py revision 12395
19793Sakash.bagdia@arm.com# Copyright (c) 2012-2013 ARM Limited 29518SAndreas.Sandberg@ARM.com# All rights reserved 311320Ssteve.reinhardt@amd.com# 49518SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59518SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69518SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79518SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89518SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99518SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109518SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119518SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129518SAndreas.Sandberg@ARM.com# 135347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 147534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 153395Shsul@eecs.umich.edu# All rights reserved. 163395Shsul@eecs.umich.edu# 173395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 183395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 193395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 203395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 213395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 223395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 233395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 243395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 253395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 263395Shsul@eecs.umich.edu# this software without specific prior written permission. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393395Shsul@eecs.umich.edu# 403395Shsul@eecs.umich.edu# Authors: Lisa Hsu 413395Shsul@eecs.umich.edu 429457Svilanova@ac.upc.eduimport sys 433395Shsul@eecs.umich.edufrom os import getcwd 443509Shsul@eecs.umich.edufrom os.path import join as joinpath 456654Snate@binkert.org 4611688Sandreas.hansson@arm.comfrom common import CpuConfig 4711688Sandreas.hansson@arm.comfrom common import MemConfig 489520SAndreas.Sandberg@ARM.com 493395Shsul@eecs.umich.eduimport m5 506654Snate@binkert.orgfrom m5.defines import buildEnv 513395Shsul@eecs.umich.edufrom m5.objects import * 526654Snate@binkert.orgfrom m5.util import * 536654Snate@binkert.org 546654Snate@binkert.orgaddToPath('../common') 553395Shsul@eecs.umich.edu 569139Snilay@cs.wisc.edudef getCPUClass(cpu_type): 579520SAndreas.Sandberg@ARM.com """Returns the required cpu class and the mode of operation.""" 589520SAndreas.Sandberg@ARM.com cls = CpuConfig.get(cpu_type) 599520SAndreas.Sandberg@ARM.com return cls, cls.memory_mode() 609139Snilay@cs.wisc.edu 613481Shsul@eecs.umich.edudef setCPUClass(options): 629139Snilay@cs.wisc.edu """Returns two cpu classes and the initial mode of operation. 633481Shsul@eecs.umich.edu 649139Snilay@cs.wisc.edu Restoring from a checkpoint or fast forwarding through a benchmark 659139Snilay@cs.wisc.edu can be done using one type of cpu, and then the actual 669139Snilay@cs.wisc.edu simulation can be carried out using another type. This function 679139Snilay@cs.wisc.edu returns these two types of cpus and the initial mode of operation 689139Snilay@cs.wisc.edu depending on the options provided. 699139Snilay@cs.wisc.edu """ 709139Snilay@cs.wisc.edu 719139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.cpu_type) 723481Shsul@eecs.umich.edu CPUClass = None 739518SAndreas.Sandberg@ARM.com if TmpClass.require_caches() and \ 749518SAndreas.Sandberg@ARM.com not options.caches and not options.ruby: 759518SAndreas.Sandberg@ARM.com fatal("%s must be used with caches" % options.cpu_type) 763481Shsul@eecs.umich.edu 779139Snilay@cs.wisc.edu if options.checkpoint_restore != None: 789139Snilay@cs.wisc.edu if options.restore_with_cpu != options.cpu_type: 793481Shsul@eecs.umich.edu CPUClass = TmpClass 809139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu) 819139Snilay@cs.wisc.edu elif options.fast_forward: 829139Snilay@cs.wisc.edu CPUClass = TmpClass 839139Snilay@cs.wisc.edu TmpClass = AtomicSimpleCPU 849139Snilay@cs.wisc.edu test_mem_mode = 'atomic' 853481Shsul@eecs.umich.edu 8612395Sswapnilster@gmail.com # Ruby only supports atomic accesses in noncaching mode 8712395Sswapnilster@gmail.com if test_mem_mode == 'atomic' and options.ruby: 8812395Sswapnilster@gmail.com warn("Memory mode will be changed to atomic_noncaching") 8912395Sswapnilster@gmail.com test_mem_mode = 'atomic_noncaching' 9012395Sswapnilster@gmail.com 913481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 923481Shsul@eecs.umich.edu 939665Sandreas.hansson@arm.comdef setMemClass(options): 949665Sandreas.hansson@arm.com """Returns a memory controller class.""" 959665Sandreas.hansson@arm.com 969665Sandreas.hansson@arm.com return MemConfig.get(options.mem_type) 979665Sandreas.hansson@arm.com 988919Snilay@cs.wisc.edudef setWorkCountOptions(system, options): 998919Snilay@cs.wisc.edu if options.work_item_id != None: 1008919Snilay@cs.wisc.edu system.work_item_id = options.work_item_id 10110159Sgedare@rtems.org if options.num_work_ids != None: 10210159Sgedare@rtems.org system.num_work_ids = options.num_work_ids 1038919Snilay@cs.wisc.edu if options.work_begin_cpu_id_exit != None: 1048919Snilay@cs.wisc.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 1058919Snilay@cs.wisc.edu if options.work_end_exit_count != None: 1068919Snilay@cs.wisc.edu system.work_end_exit_count = options.work_end_exit_count 1078919Snilay@cs.wisc.edu if options.work_end_checkpoint_count != None: 1088919Snilay@cs.wisc.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 1098919Snilay@cs.wisc.edu if options.work_begin_exit_count != None: 1108919Snilay@cs.wisc.edu system.work_begin_exit_count = options.work_begin_exit_count 1118919Snilay@cs.wisc.edu if options.work_begin_checkpoint_count != None: 1128919Snilay@cs.wisc.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 1138919Snilay@cs.wisc.edu if options.work_cpus_checkpoint_count != None: 1148919Snilay@cs.wisc.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 1153481Shsul@eecs.umich.edu 1169816Sjthestness@gmail.comdef findCptDir(options, cptdir, testsys): 1179140Snilay@cs.wisc.edu """Figures out the directory from which the checkpointed state is read. 1189140Snilay@cs.wisc.edu 1199140Snilay@cs.wisc.edu There are two different ways in which the directories holding checkpoints 1209140Snilay@cs.wisc.edu can be named -- 1219140Snilay@cs.wisc.edu 1. cpt.<benchmark name>.<instruction count when the checkpoint was taken> 1229140Snilay@cs.wisc.edu 2. cpt.<some number, usually the tick value when the checkpoint was taken> 1239140Snilay@cs.wisc.edu 1249140Snilay@cs.wisc.edu This function parses through the options to figure out which one of the 1259140Snilay@cs.wisc.edu above should be used for selecting the checkpoint, and then figures out 1269140Snilay@cs.wisc.edu the appropriate directory. 1279140Snilay@cs.wisc.edu """ 1289140Snilay@cs.wisc.edu 1299140Snilay@cs.wisc.edu from os.path import isdir, exists 1309140Snilay@cs.wisc.edu from os import listdir 1319140Snilay@cs.wisc.edu import re 1329140Snilay@cs.wisc.edu 1339140Snilay@cs.wisc.edu if not isdir(cptdir): 1349140Snilay@cs.wisc.edu fatal("checkpoint dir %s does not exist!", cptdir) 1359140Snilay@cs.wisc.edu 1369867Sjthestness@gmail.com cpt_starttick = 0 1379140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1389140Snilay@cs.wisc.edu inst = options.checkpoint_restore 1399140Snilay@cs.wisc.edu if options.simpoint: 1409140Snilay@cs.wisc.edu # assume workload 0 has the simpoint 1419140Snilay@cs.wisc.edu if testsys.cpu[0].workload[0].simpoint == 0: 1429140Snilay@cs.wisc.edu fatal('Unable to find simpoint') 1439140Snilay@cs.wisc.edu inst += int(testsys.cpu[0].workload[0].simpoint) 1449140Snilay@cs.wisc.edu 1459140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) 1469140Snilay@cs.wisc.edu if not exists(checkpoint_dir): 1479140Snilay@cs.wisc.edu fatal("Unable to find checkpoint directory %s", checkpoint_dir) 14810608Sdam.sunwoo@arm.com 14910608Sdam.sunwoo@arm.com elif options.restore_simpoint_checkpoint: 15010608Sdam.sunwoo@arm.com # Restore from SimPoint checkpoints 15110608Sdam.sunwoo@arm.com # Assumes that the checkpoint dir names are formatted as follows: 15210608Sdam.sunwoo@arm.com dirs = listdir(cptdir) 15310608Sdam.sunwoo@arm.com expr = re.compile('cpt\.simpoint_(\d+)_inst_(\d+)' + 15410608Sdam.sunwoo@arm.com '_weight_([\d\.e\-]+)_interval_(\d+)_warmup_(\d+)') 15510608Sdam.sunwoo@arm.com cpts = [] 15610608Sdam.sunwoo@arm.com for dir in dirs: 15710608Sdam.sunwoo@arm.com match = expr.match(dir) 15810608Sdam.sunwoo@arm.com if match: 15910608Sdam.sunwoo@arm.com cpts.append(dir) 16010608Sdam.sunwoo@arm.com cpts.sort() 16110608Sdam.sunwoo@arm.com 16210608Sdam.sunwoo@arm.com cpt_num = options.checkpoint_restore 16310608Sdam.sunwoo@arm.com if cpt_num > len(cpts): 16410608Sdam.sunwoo@arm.com fatal('Checkpoint %d not found', cpt_num) 16510608Sdam.sunwoo@arm.com checkpoint_dir = joinpath(cptdir, cpts[cpt_num - 1]) 16610608Sdam.sunwoo@arm.com match = expr.match(cpts[cpt_num - 1]) 16710608Sdam.sunwoo@arm.com if match: 16810608Sdam.sunwoo@arm.com index = int(match.group(1)) 16910608Sdam.sunwoo@arm.com start_inst = int(match.group(2)) 17010608Sdam.sunwoo@arm.com weight_inst = float(match.group(3)) 17110608Sdam.sunwoo@arm.com interval_length = int(match.group(4)) 17210608Sdam.sunwoo@arm.com warmup_length = int(match.group(5)) 17310608Sdam.sunwoo@arm.com print "Resuming from", checkpoint_dir 17410608Sdam.sunwoo@arm.com simpoint_start_insts = [] 17510608Sdam.sunwoo@arm.com simpoint_start_insts.append(warmup_length) 17610608Sdam.sunwoo@arm.com simpoint_start_insts.append(warmup_length + interval_length) 17710608Sdam.sunwoo@arm.com testsys.cpu[0].simpoint_start_insts = simpoint_start_insts 17810608Sdam.sunwoo@arm.com if testsys.switch_cpus != None: 17910608Sdam.sunwoo@arm.com testsys.switch_cpus[0].simpoint_start_insts = simpoint_start_insts 18010608Sdam.sunwoo@arm.com 18110608Sdam.sunwoo@arm.com print "Resuming from SimPoint", 18210608Sdam.sunwoo@arm.com print "#%d, start_inst:%d, weight:%f, interval:%d, warmup:%d" % \ 18310608Sdam.sunwoo@arm.com (index, start_inst, weight_inst, interval_length, warmup_length) 18410608Sdam.sunwoo@arm.com 1859140Snilay@cs.wisc.edu else: 1869140Snilay@cs.wisc.edu dirs = listdir(cptdir) 18710608Sdam.sunwoo@arm.com expr = re.compile('cpt\.([0-9]+)') 1889140Snilay@cs.wisc.edu cpts = [] 1899140Snilay@cs.wisc.edu for dir in dirs: 1909140Snilay@cs.wisc.edu match = expr.match(dir) 1919140Snilay@cs.wisc.edu if match: 1929140Snilay@cs.wisc.edu cpts.append(match.group(1)) 1939140Snilay@cs.wisc.edu 1949140Snilay@cs.wisc.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 1959140Snilay@cs.wisc.edu 1969140Snilay@cs.wisc.edu cpt_num = options.checkpoint_restore 1979140Snilay@cs.wisc.edu if cpt_num > len(cpts): 1989140Snilay@cs.wisc.edu fatal('Checkpoint %d not found', cpt_num) 1999140Snilay@cs.wisc.edu 2009816Sjthestness@gmail.com cpt_starttick = int(cpts[cpt_num - 1]) 2019140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 2029140Snilay@cs.wisc.edu 2039816Sjthestness@gmail.com return cpt_starttick, checkpoint_dir 2049140Snilay@cs.wisc.edu 2059215Sandreas.hansson@arm.comdef scriptCheckpoints(options, maxtick, cptdir): 2069140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 2079140Snilay@cs.wisc.edu checkpoint_inst = int(options.take_checkpoints) 2089140Snilay@cs.wisc.edu 2099140Snilay@cs.wisc.edu # maintain correct offset if we restored from some instruction 2109140Snilay@cs.wisc.edu if options.checkpoint_restore != None: 2119140Snilay@cs.wisc.edu checkpoint_inst += options.checkpoint_restore 2129140Snilay@cs.wisc.edu 2139140Snilay@cs.wisc.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 2149140Snilay@cs.wisc.edu exit_event = m5.simulate() 2159140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2169140Snilay@cs.wisc.edu print "exit cause = %s" % exit_cause 2179140Snilay@cs.wisc.edu 2189140Snilay@cs.wisc.edu # skip checkpoint instructions should they exist 2199140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2209140Snilay@cs.wisc.edu exit_event = m5.simulate() 2219140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2229140Snilay@cs.wisc.edu 2239140Snilay@cs.wisc.edu if exit_cause == "a thread reached the max instruction count": 2249140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 2259140Snilay@cs.wisc.edu (options.bench, checkpoint_inst))) 2269140Snilay@cs.wisc.edu print "Checkpoint written." 2279140Snilay@cs.wisc.edu 2289140Snilay@cs.wisc.edu else: 2299140Snilay@cs.wisc.edu when, period = options.take_checkpoints.split(",", 1) 2309140Snilay@cs.wisc.edu when = int(when) 2319140Snilay@cs.wisc.edu period = int(period) 2329156Sandreas.hansson@arm.com num_checkpoints = 0 2339140Snilay@cs.wisc.edu 2349634Sjthestness@gmail.com exit_event = m5.simulate(when - m5.curTick()) 2359140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2369140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2379140Snilay@cs.wisc.edu exit_event = m5.simulate(when - m5.curTick()) 2389140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2399140Snilay@cs.wisc.edu 2409140Snilay@cs.wisc.edu if exit_cause == "simulate() limit reached": 2419140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2429140Snilay@cs.wisc.edu num_checkpoints += 1 2439140Snilay@cs.wisc.edu 2449140Snilay@cs.wisc.edu sim_ticks = when 2459140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2469140Snilay@cs.wisc.edu 2479140Snilay@cs.wisc.edu while num_checkpoints < max_checkpoints and \ 2489140Snilay@cs.wisc.edu exit_cause == "simulate() limit reached": 2499140Snilay@cs.wisc.edu if (sim_ticks + period) > maxtick: 2509140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - sim_ticks) 2519140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2529140Snilay@cs.wisc.edu break 2539140Snilay@cs.wisc.edu else: 2549140Snilay@cs.wisc.edu exit_event = m5.simulate(period) 2559140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2569140Snilay@cs.wisc.edu sim_ticks += period 2579140Snilay@cs.wisc.edu while exit_event.getCause() == "checkpoint": 2589140Snilay@cs.wisc.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 2599140Snilay@cs.wisc.edu if exit_event.getCause() == "simulate() limit reached": 2609140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2619140Snilay@cs.wisc.edu num_checkpoints += 1 2629140Snilay@cs.wisc.edu 2639606Snilay@cs.wisc.edu return exit_event 2649140Snilay@cs.wisc.edu 2659140Snilay@cs.wisc.edudef benchCheckpoints(options, maxtick, cptdir): 2669634Sjthestness@gmail.com exit_event = m5.simulate(maxtick - m5.curTick()) 2679140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2689140Snilay@cs.wisc.edu 2699140Snilay@cs.wisc.edu num_checkpoints = 0 2709140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2719140Snilay@cs.wisc.edu 2729140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2739140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2749140Snilay@cs.wisc.edu num_checkpoints += 1 2759140Snilay@cs.wisc.edu if num_checkpoints == max_checkpoints: 2769140Snilay@cs.wisc.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 2779140Snilay@cs.wisc.edu break 2789140Snilay@cs.wisc.edu 2799140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2809140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2819140Snilay@cs.wisc.edu 2829460Ssaidi@eecs.umich.edu return exit_event 2839140Snilay@cs.wisc.edu 28410608Sdam.sunwoo@arm.com# Set up environment for taking SimPoint checkpoints 28510608Sdam.sunwoo@arm.com# Expecting SimPoint files generated by SimPoint 3.2 28610608Sdam.sunwoo@arm.comdef parseSimpointAnalysisFile(options, testsys): 28710608Sdam.sunwoo@arm.com import re 28810608Sdam.sunwoo@arm.com 28910608Sdam.sunwoo@arm.com simpoint_filename, weight_filename, interval_length, warmup_length = \ 29010608Sdam.sunwoo@arm.com options.take_simpoint_checkpoints.split(",", 3) 29110608Sdam.sunwoo@arm.com print "simpoint analysis file:", simpoint_filename 29210608Sdam.sunwoo@arm.com print "simpoint weight file:", weight_filename 29310608Sdam.sunwoo@arm.com print "interval length:", interval_length 29410608Sdam.sunwoo@arm.com print "warmup length:", warmup_length 29510608Sdam.sunwoo@arm.com 29610608Sdam.sunwoo@arm.com interval_length = int(interval_length) 29710608Sdam.sunwoo@arm.com warmup_length = int(warmup_length) 29810608Sdam.sunwoo@arm.com 29910608Sdam.sunwoo@arm.com # Simpoint analysis output starts interval counts with 0. 30010608Sdam.sunwoo@arm.com simpoints = [] 30110608Sdam.sunwoo@arm.com simpoint_start_insts = [] 30210608Sdam.sunwoo@arm.com 30310608Sdam.sunwoo@arm.com # Read in SimPoint analysis files 30410608Sdam.sunwoo@arm.com simpoint_file = open(simpoint_filename) 30510608Sdam.sunwoo@arm.com weight_file = open(weight_filename) 30610608Sdam.sunwoo@arm.com while True: 30710608Sdam.sunwoo@arm.com line = simpoint_file.readline() 30810608Sdam.sunwoo@arm.com if not line: 30910608Sdam.sunwoo@arm.com break 31010608Sdam.sunwoo@arm.com m = re.match("(\d+)\s+(\d+)", line) 31110608Sdam.sunwoo@arm.com if m: 31210608Sdam.sunwoo@arm.com interval = int(m.group(1)) 31310608Sdam.sunwoo@arm.com else: 31410608Sdam.sunwoo@arm.com fatal('unrecognized line in simpoint file!') 31510608Sdam.sunwoo@arm.com 31610608Sdam.sunwoo@arm.com line = weight_file.readline() 31710608Sdam.sunwoo@arm.com if not line: 31810608Sdam.sunwoo@arm.com fatal('not enough lines in simpoint weight file!') 31910608Sdam.sunwoo@arm.com m = re.match("([0-9\.e\-]+)\s+(\d+)", line) 32010608Sdam.sunwoo@arm.com if m: 32110608Sdam.sunwoo@arm.com weight = float(m.group(1)) 32210608Sdam.sunwoo@arm.com else: 32310608Sdam.sunwoo@arm.com fatal('unrecognized line in simpoint weight file!') 32410608Sdam.sunwoo@arm.com 32510608Sdam.sunwoo@arm.com if (interval * interval_length - warmup_length > 0): 32610608Sdam.sunwoo@arm.com starting_inst_count = \ 32710608Sdam.sunwoo@arm.com interval * interval_length - warmup_length 32810608Sdam.sunwoo@arm.com actual_warmup_length = warmup_length 32910608Sdam.sunwoo@arm.com else: 33010608Sdam.sunwoo@arm.com # Not enough room for proper warmup 33110608Sdam.sunwoo@arm.com # Just starting from the beginning 33210608Sdam.sunwoo@arm.com starting_inst_count = 0 33310608Sdam.sunwoo@arm.com actual_warmup_length = interval * interval_length 33410608Sdam.sunwoo@arm.com 33510608Sdam.sunwoo@arm.com simpoints.append((interval, weight, starting_inst_count, 33610608Sdam.sunwoo@arm.com actual_warmup_length)) 33710608Sdam.sunwoo@arm.com 33810608Sdam.sunwoo@arm.com # Sort SimPoints by starting inst count 33910608Sdam.sunwoo@arm.com simpoints.sort(key=lambda obj: obj[2]) 34010608Sdam.sunwoo@arm.com for s in simpoints: 34110608Sdam.sunwoo@arm.com interval, weight, starting_inst_count, actual_warmup_length = s 34210608Sdam.sunwoo@arm.com print str(interval), str(weight), starting_inst_count, \ 34310608Sdam.sunwoo@arm.com actual_warmup_length 34410608Sdam.sunwoo@arm.com simpoint_start_insts.append(starting_inst_count) 34510608Sdam.sunwoo@arm.com 34610608Sdam.sunwoo@arm.com print "Total # of simpoints:", len(simpoints) 34710608Sdam.sunwoo@arm.com testsys.cpu[0].simpoint_start_insts = simpoint_start_insts 34810608Sdam.sunwoo@arm.com 34910608Sdam.sunwoo@arm.com return (simpoints, interval_length) 35010608Sdam.sunwoo@arm.com 35110608Sdam.sunwoo@arm.comdef takeSimpointCheckpoints(simpoints, interval_length, cptdir): 35210608Sdam.sunwoo@arm.com num_checkpoints = 0 35310608Sdam.sunwoo@arm.com index = 0 35410608Sdam.sunwoo@arm.com last_chkpnt_inst_count = -1 35510608Sdam.sunwoo@arm.com for simpoint in simpoints: 35610608Sdam.sunwoo@arm.com interval, weight, starting_inst_count, actual_warmup_length = simpoint 35710608Sdam.sunwoo@arm.com if starting_inst_count == last_chkpnt_inst_count: 35810608Sdam.sunwoo@arm.com # checkpoint starting point same as last time 35910608Sdam.sunwoo@arm.com # (when warmup period longer than starting point) 36010608Sdam.sunwoo@arm.com exit_cause = "simpoint starting point found" 36110608Sdam.sunwoo@arm.com code = 0 36210608Sdam.sunwoo@arm.com else: 36310608Sdam.sunwoo@arm.com exit_event = m5.simulate() 36410608Sdam.sunwoo@arm.com 36510608Sdam.sunwoo@arm.com # skip checkpoint instructions should they exist 36610608Sdam.sunwoo@arm.com while exit_event.getCause() == "checkpoint": 36710608Sdam.sunwoo@arm.com print "Found 'checkpoint' exit event...ignoring..." 36810608Sdam.sunwoo@arm.com exit_event = m5.simulate() 36910608Sdam.sunwoo@arm.com 37010608Sdam.sunwoo@arm.com exit_cause = exit_event.getCause() 37110608Sdam.sunwoo@arm.com code = exit_event.getCode() 37210608Sdam.sunwoo@arm.com 37310608Sdam.sunwoo@arm.com if exit_cause == "simpoint starting point found": 37410608Sdam.sunwoo@arm.com m5.checkpoint(joinpath(cptdir, 37510608Sdam.sunwoo@arm.com "cpt.simpoint_%02d_inst_%d_weight_%f_interval_%d_warmup_%d" 37610608Sdam.sunwoo@arm.com % (index, starting_inst_count, weight, interval_length, 37710608Sdam.sunwoo@arm.com actual_warmup_length))) 37810608Sdam.sunwoo@arm.com print "Checkpoint #%d written. start inst:%d weight:%f" % \ 37910608Sdam.sunwoo@arm.com (num_checkpoints, starting_inst_count, weight) 38010608Sdam.sunwoo@arm.com num_checkpoints += 1 38110608Sdam.sunwoo@arm.com last_chkpnt_inst_count = starting_inst_count 38210608Sdam.sunwoo@arm.com else: 38310608Sdam.sunwoo@arm.com break 38410608Sdam.sunwoo@arm.com index += 1 38510608Sdam.sunwoo@arm.com 38610608Sdam.sunwoo@arm.com print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 38710608Sdam.sunwoo@arm.com print "%d checkpoints taken" % num_checkpoints 38810608Sdam.sunwoo@arm.com sys.exit(code) 38910608Sdam.sunwoo@arm.com 39010608Sdam.sunwoo@arm.comdef restoreSimpointCheckpoint(): 39110608Sdam.sunwoo@arm.com exit_event = m5.simulate() 39210608Sdam.sunwoo@arm.com exit_cause = exit_event.getCause() 39310608Sdam.sunwoo@arm.com 39410608Sdam.sunwoo@arm.com if exit_cause == "simpoint starting point found": 39510608Sdam.sunwoo@arm.com print "Warmed up! Dumping and resetting stats!" 39610608Sdam.sunwoo@arm.com m5.stats.dump() 39710608Sdam.sunwoo@arm.com m5.stats.reset() 39810608Sdam.sunwoo@arm.com 39910608Sdam.sunwoo@arm.com exit_event = m5.simulate() 40010608Sdam.sunwoo@arm.com exit_cause = exit_event.getCause() 40110608Sdam.sunwoo@arm.com 40210608Sdam.sunwoo@arm.com if exit_cause == "simpoint starting point found": 40310608Sdam.sunwoo@arm.com print "Done running SimPoint!" 40410608Sdam.sunwoo@arm.com sys.exit(exit_event.getCode()) 40510608Sdam.sunwoo@arm.com 40610608Sdam.sunwoo@arm.com print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 40710608Sdam.sunwoo@arm.com sys.exit(exit_event.getCode()) 40810608Sdam.sunwoo@arm.com 4099151Satgutier@umich.edudef repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, switch_freq): 4109151Satgutier@umich.edu print "starting switch loop" 4119151Satgutier@umich.edu while True: 4129151Satgutier@umich.edu exit_event = m5.simulate(switch_freq) 4139151Satgutier@umich.edu exit_cause = exit_event.getCause() 4149151Satgutier@umich.edu 4159151Satgutier@umich.edu if exit_cause != "simulate() limit reached": 4169460Ssaidi@eecs.umich.edu return exit_event 4179151Satgutier@umich.edu 4189521SAndreas.Sandberg@ARM.com m5.switchCpus(testsys, repeat_switch_cpu_list) 4199151Satgutier@umich.edu 4209151Satgutier@umich.edu tmp_cpu_list = [] 4219151Satgutier@umich.edu for old_cpu, new_cpu in repeat_switch_cpu_list: 4229151Satgutier@umich.edu tmp_cpu_list.append((new_cpu, old_cpu)) 4239151Satgutier@umich.edu repeat_switch_cpu_list = tmp_cpu_list 4249151Satgutier@umich.edu 4259151Satgutier@umich.edu if (maxtick - m5.curTick()) <= switch_freq: 4269151Satgutier@umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 4279460Ssaidi@eecs.umich.edu return exit_event 4289151Satgutier@umich.edu 4293481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 4303395Shsul@eecs.umich.edu if options.checkpoint_dir: 4313395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 4325211Ssaidi@eecs.umich.edu elif m5.options.outdir: 4335211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 4343395Shsul@eecs.umich.edu else: 4353395Shsul@eecs.umich.edu cptdir = getcwd() 4363395Shsul@eecs.umich.edu 4375370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 4386654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 4395370Ssaidi@eecs.umich.edu 4405371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 4416654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 4425370Ssaidi@eecs.umich.edu 4439151Satgutier@umich.edu if options.standard_switch and options.repeat_switch: 4449151Satgutier@umich.edu fatal("Can't specify both --standard-switch and --repeat-switch") 4459151Satgutier@umich.edu 4469151Satgutier@umich.edu if options.repeat_switch and options.take_checkpoints: 4479151Satgutier@umich.edu fatal("Can't specify both --repeat-switch and --take-checkpoints") 4489151Satgutier@umich.edu 4493395Shsul@eecs.umich.edu np = options.num_cpus 4503481Shsul@eecs.umich.edu switch_cpus = None 4513481Shsul@eecs.umich.edu 4528318Sksewell@umich.edu if options.prog_interval: 4536144Sksewell@umich.edu for i in xrange(np): 4548311Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_interval 4556144Sksewell@umich.edu 4566641Sksewell@umich.edu if options.maxinsts: 4576641Sksewell@umich.edu for i in xrange(np): 4586641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 4596641Sksewell@umich.edu 4603481Shsul@eecs.umich.edu if cpu_class: 4619433SAndreas.Sandberg@ARM.com switch_cpus = [cpu_class(switched_out=True, cpu_id=(i)) 4623481Shsul@eecs.umich.edu for i in xrange(np)] 4633481Shsul@eecs.umich.edu 4643481Shsul@eecs.umich.edu for i in xrange(np): 4655361Srstrong@cs.ucsd.edu if options.fast_forward: 4665369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 46711251Sradhika.jagtap@ARM.com switch_cpus[i].system = testsys 4688803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 4699793Sakash.bagdia@arm.com switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain 47011251Sradhika.jagtap@ARM.com switch_cpus[i].progress_interval = \ 47111251Sradhika.jagtap@ARM.com testsys.cpu[i].progress_interval 47212374Saustinharris@utexas.edu switch_cpus[i].isa = testsys.cpu[i].isa 4735369Ssaidi@eecs.umich.edu # simulation period 4748311Sksewell@umich.edu if options.maxinsts: 4758311Sksewell@umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 4768887Sgeoffrey.blake@arm.com # Add checker cpu if selected 4778887Sgeoffrey.blake@arm.com if options.checker: 4788887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 4793481Shsul@eecs.umich.edu 48011251Sradhika.jagtap@ARM.com # If elastic tracing is enabled attach the elastic trace probe 48111251Sradhika.jagtap@ARM.com # to the switch CPUs 48211251Sradhika.jagtap@ARM.com if options.elastic_trace_en: 48311251Sradhika.jagtap@ARM.com CpuConfig.config_etrace(cpu_class, switch_cpus, options) 48411251Sradhika.jagtap@ARM.com 4855311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 4863481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 4873395Shsul@eecs.umich.edu 4889151Satgutier@umich.edu if options.repeat_switch: 4899518SAndreas.Sandberg@ARM.com switch_class = getCPUClass(options.cpu_type)[0] 4909518SAndreas.Sandberg@ARM.com if switch_class.require_caches() and \ 4919518SAndreas.Sandberg@ARM.com not options.caches: 4929518SAndreas.Sandberg@ARM.com print "%s: Must be used with caches" % str(switch_class) 4939518SAndreas.Sandberg@ARM.com sys.exit(1) 4949518SAndreas.Sandberg@ARM.com if not switch_class.support_take_over(): 4959518SAndreas.Sandberg@ARM.com print "%s: CPU switching not supported" % str(switch_class) 4969518SAndreas.Sandberg@ARM.com sys.exit(1) 4979151Satgutier@umich.edu 4989518SAndreas.Sandberg@ARM.com repeat_switch_cpus = [switch_class(switched_out=True, \ 4999518SAndreas.Sandberg@ARM.com cpu_id=(i)) for i in xrange(np)] 5009151Satgutier@umich.edu 5019151Satgutier@umich.edu for i in xrange(np): 5029151Satgutier@umich.edu repeat_switch_cpus[i].system = testsys 5039151Satgutier@umich.edu repeat_switch_cpus[i].workload = testsys.cpu[i].workload 5049793Sakash.bagdia@arm.com repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain 50512374Saustinharris@utexas.edu repeat_switch_cpus[i].isa = testsys.cpu[i].isa 5069151Satgutier@umich.edu 5079151Satgutier@umich.edu if options.maxinsts: 5089151Satgutier@umich.edu repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts 5099151Satgutier@umich.edu 5109151Satgutier@umich.edu if options.checker: 5119151Satgutier@umich.edu repeat_switch_cpus[i].addCheckerCpu() 5129151Satgutier@umich.edu 5139151Satgutier@umich.edu testsys.repeat_switch_cpus = repeat_switch_cpus 5149151Satgutier@umich.edu 5159151Satgutier@umich.edu if cpu_class: 5169151Satgutier@umich.edu repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) 5179151Satgutier@umich.edu for i in xrange(np)] 5189151Satgutier@umich.edu else: 5199151Satgutier@umich.edu repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) 5209151Satgutier@umich.edu for i in xrange(np)] 5219151Satgutier@umich.edu 5223395Shsul@eecs.umich.edu if options.standard_switch: 5239433SAndreas.Sandberg@ARM.com switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i)) 5243395Shsul@eecs.umich.edu for i in xrange(np)] 5259433SAndreas.Sandberg@ARM.com switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i)) 5263395Shsul@eecs.umich.edu for i in xrange(np)] 5273478Shsul@eecs.umich.edu 5283395Shsul@eecs.umich.edu for i in xrange(np): 5293395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 5303478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 5318803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 5328803Sgblack@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 5339793Sakash.bagdia@arm.com switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain 5349793Sakash.bagdia@arm.com switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain 53512374Saustinharris@utexas.edu switch_cpus[i].isa = testsys.cpu[i].isa 53612374Saustinharris@utexas.edu switch_cpus_1[i].isa = testsys.cpu[i].isa 5373480Shsul@eecs.umich.edu 5385361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 5395369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 5405361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 5415361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 5425361Srstrong@cs.ucsd.edu elif options.fast_forward: 5435369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 5445361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 5455361Srstrong@cs.ucsd.edu elif options.simpoint: 5465378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 5476654Snate@binkert.org fatal('simpoint not found') 5485361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 5495361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 5505361Srstrong@cs.ucsd.edu # No distance specified, just switch 5515361Srstrong@cs.ucsd.edu else: 5525361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 5535361Srstrong@cs.ucsd.edu 5545361Srstrong@cs.ucsd.edu # warmup period 5555361Srstrong@cs.ucsd.edu if options.warmup_insts: 5565361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 5575361Srstrong@cs.ucsd.edu 5585361Srstrong@cs.ucsd.edu # simulation period 5598311Sksewell@umich.edu if options.maxinsts: 5608311Sksewell@umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 5615353Svilas.sridharan@gmail.com 5628887Sgeoffrey.blake@arm.com # attach the checker cpu if selected 5638887Sgeoffrey.blake@arm.com if options.checker: 5648887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 5658887Sgeoffrey.blake@arm.com switch_cpus_1[i].addCheckerCpu() 5668887Sgeoffrey.blake@arm.com 5678211Satgutier@umich.edu testsys.switch_cpus = switch_cpus 5688211Satgutier@umich.edu testsys.switch_cpus_1 = switch_cpus_1 5698211Satgutier@umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 5708211Satgutier@umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 5713395Shsul@eecs.umich.edu 5725361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 5735369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 5745361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 5755361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 5765361Srstrong@cs.ucsd.edu # Set an instruction break point 5775361Srstrong@cs.ucsd.edu if options.simpoint: 5785361Srstrong@cs.ucsd.edu for i in xrange(np): 5795378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 5806654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 5815369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 5825361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 5835361Srstrong@cs.ucsd.edu # used for output below 5845361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 5855361Srstrong@cs.ucsd.edu else: 5865361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 5875361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 5885361Srstrong@cs.ucsd.edu # for the upcoming simulation 5895361Srstrong@cs.ucsd.edu for i in xrange(np): 5905361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 5915361Srstrong@cs.ucsd.edu 59210608Sdam.sunwoo@arm.com if options.take_simpoint_checkpoints != None: 59310608Sdam.sunwoo@arm.com simpoints, interval_length = parseSimpointAnalysisFile(options, testsys) 59410608Sdam.sunwoo@arm.com 5957531Ssteve.reinhardt@amd.com checkpoint_dir = None 5969816Sjthestness@gmail.com if options.checkpoint_restore: 5979816Sjthestness@gmail.com cpt_starttick, checkpoint_dir = findCptDir(options, cptdir, testsys) 5987531Ssteve.reinhardt@amd.com m5.instantiate(checkpoint_dir) 5993395Shsul@eecs.umich.edu 60010757SCurtis.Dunham@arm.com # Initialization is complete. If we're not in control of simulation 60110757SCurtis.Dunham@arm.com # (that is, if we're a slave simulator acting as a component in another 60210757SCurtis.Dunham@arm.com # 'master' simulator) then we're done here. The other simulator will 60310757SCurtis.Dunham@arm.com # call simulate() directly. --initialize-only is used to indicate this. 60410757SCurtis.Dunham@arm.com if options.initialize_only: 60510757SCurtis.Dunham@arm.com return 60610757SCurtis.Dunham@arm.com 6079816Sjthestness@gmail.com # Handle the max tick settings now that tick frequency was resolved 6089816Sjthestness@gmail.com # during system instantiation 6099816Sjthestness@gmail.com # NOTE: the maxtick variable here is in absolute ticks, so it must 6109816Sjthestness@gmail.com # include any simulated ticks before a checkpoint 6119816Sjthestness@gmail.com explicit_maxticks = 0 6129816Sjthestness@gmail.com maxtick_from_abs = m5.MaxTick 6139816Sjthestness@gmail.com maxtick_from_rel = m5.MaxTick 6149816Sjthestness@gmail.com maxtick_from_maxtime = m5.MaxTick 6159816Sjthestness@gmail.com if options.abs_max_tick: 6169816Sjthestness@gmail.com maxtick_from_abs = options.abs_max_tick 6179816Sjthestness@gmail.com explicit_maxticks += 1 6189816Sjthestness@gmail.com if options.rel_max_tick: 6199816Sjthestness@gmail.com maxtick_from_rel = options.rel_max_tick 6209816Sjthestness@gmail.com if options.checkpoint_restore: 6219816Sjthestness@gmail.com # NOTE: this may need to be updated if checkpoints ever store 6229816Sjthestness@gmail.com # the ticks per simulated second 6239816Sjthestness@gmail.com maxtick_from_rel += cpt_starttick 6249867Sjthestness@gmail.com if options.at_instruction or options.simpoint: 6259867Sjthestness@gmail.com warn("Relative max tick specified with --at-instruction or" \ 6269867Sjthestness@gmail.com " --simpoint\n These options don't specify the " \ 6279867Sjthestness@gmail.com "checkpoint start tick, so assuming\n you mean " \ 6289867Sjthestness@gmail.com "absolute max tick") 6299816Sjthestness@gmail.com explicit_maxticks += 1 6309816Sjthestness@gmail.com if options.maxtime: 6319816Sjthestness@gmail.com maxtick_from_maxtime = m5.ticks.fromSeconds(options.maxtime) 6329816Sjthestness@gmail.com explicit_maxticks += 1 6339816Sjthestness@gmail.com if explicit_maxticks > 1: 6349816Sjthestness@gmail.com warn("Specified multiple of --abs-max-tick, --rel-max-tick, --maxtime."\ 6359816Sjthestness@gmail.com " Using least") 6369816Sjthestness@gmail.com maxtick = min([maxtick_from_abs, maxtick_from_rel, maxtick_from_maxtime]) 6379816Sjthestness@gmail.com 6389816Sjthestness@gmail.com if options.checkpoint_restore != None and maxtick < cpt_starttick: 6399816Sjthestness@gmail.com fatal("Bad maxtick (%d) specified: " \ 6409816Sjthestness@gmail.com "Checkpoint starts starts from tick: %d", maxtick, cpt_starttick) 6419816Sjthestness@gmail.com 6423481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 6435361Srstrong@cs.ucsd.edu if options.standard_switch: 6445361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 6455361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 6465361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 6475361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 6485361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 6495361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 6505361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 6515361Srstrong@cs.ucsd.edu else: 6525361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 6535361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 6547766Sgblack@eecs.umich.edu print "Switched CPUS @ tick %s" % (m5.curTick()) 6553395Shsul@eecs.umich.edu 6569521SAndreas.Sandberg@ARM.com m5.switchCpus(testsys, switch_cpu_list) 6573395Shsul@eecs.umich.edu 6583481Shsul@eecs.umich.edu if options.standard_switch: 6595361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 6605361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 6615361Srstrong@cs.ucsd.edu 6625361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 6635361Srstrong@cs.ucsd.edu if options.warmup_insts: 6645361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 6655361Srstrong@cs.ucsd.edu else: 6669151Satgutier@umich.edu exit_event = m5.simulate(options.standard_switch) 6677766Sgblack@eecs.umich.edu print "Switching CPUS @ tick %s" % (m5.curTick()) 6685361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 6695361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 6709521SAndreas.Sandberg@ARM.com m5.switchCpus(testsys, switch_cpu_list1) 6713395Shsul@eecs.umich.edu 6727489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 6737489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 6747489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 6757489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 67610608Sdam.sunwoo@arm.com if (options.take_checkpoints or options.take_simpoint_checkpoints) \ 67710608Sdam.sunwoo@arm.com and options.checkpoint_restore: 67810608Sdam.sunwoo@arm.com 6797489Ssteve.reinhardt@amd.com if m5.options.outdir: 6807489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 6817489Ssteve.reinhardt@amd.com else: 6827489Ssteve.reinhardt@amd.com cptdir = getcwd() 6837489Ssteve.reinhardt@amd.com 6845369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 6859140Snilay@cs.wisc.edu # Checkpoints being taken via the command line at <when> and at 6869140Snilay@cs.wisc.edu # subsequent periods of <period>. Checkpoint instructions 6879140Snilay@cs.wisc.edu # received from the benchmark running are ignored and skipped in 6889140Snilay@cs.wisc.edu # favor of command line checkpoint instructions. 6899606Snilay@cs.wisc.edu exit_event = scriptCheckpoints(options, maxtick, cptdir) 69010608Sdam.sunwoo@arm.com 69110608Sdam.sunwoo@arm.com # Take SimPoint checkpoints 69210608Sdam.sunwoo@arm.com elif options.take_simpoint_checkpoints != None: 69310608Sdam.sunwoo@arm.com takeSimpointCheckpoints(simpoints, interval_length, cptdir) 69410608Sdam.sunwoo@arm.com 69510608Sdam.sunwoo@arm.com # Restore from SimPoint checkpoints 69610608Sdam.sunwoo@arm.com elif options.restore_simpoint_checkpoint != None: 69710608Sdam.sunwoo@arm.com restoreSimpointCheckpoint() 69810608Sdam.sunwoo@arm.com 6999140Snilay@cs.wisc.edu else: 7009151Satgutier@umich.edu if options.fast_forward: 7019151Satgutier@umich.edu m5.stats.reset() 7029151Satgutier@umich.edu print "**** REAL SIMULATION ****" 7039151Satgutier@umich.edu 7049140Snilay@cs.wisc.edu # If checkpoints are being taken, then the checkpoint instruction 7059140Snilay@cs.wisc.edu # will occur in the benchmark code it self. 7069151Satgutier@umich.edu if options.repeat_switch and maxtick > options.repeat_switch: 7079460Ssaidi@eecs.umich.edu exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, 7089151Satgutier@umich.edu maxtick, options.repeat_switch) 7099151Satgutier@umich.edu else: 7109460Ssaidi@eecs.umich.edu exit_event = benchCheckpoints(options, maxtick, cptdir) 7113395Shsul@eecs.umich.edu 7129460Ssaidi@eecs.umich.edu print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) 7136776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 7147525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 7159457Svilanova@ac.upc.edu 7169494Sandreas@sandberg.pp.se if not m5.options.interactive: 7179494Sandreas@sandberg.pp.se sys.exit(exit_event.getCode()) 718