Options.py revision 3395
12650Ssaidi@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 22650Ssaidi@eecs.umich.edu# All rights reserved. 32650Ssaidi@eecs.umich.edu# 42650Ssaidi@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 52650Ssaidi@eecs.umich.edu# modification, are permitted provided that the following conditions are 62650Ssaidi@eecs.umich.edu# met: redistributions of source code must retain the above copyright 72650Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 82650Ssaidi@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 92650Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 102650Ssaidi@eecs.umich.edu# documentation and/or other materials provided with the distribution; 112650Ssaidi@eecs.umich.edu# neither the name of the copyright holders nor the names of its 122650Ssaidi@eecs.umich.edu# contributors may be used to endorse or promote products derived from 132650Ssaidi@eecs.umich.edu# this software without specific prior written permission. 142650Ssaidi@eecs.umich.edu# 152650Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162650Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172650Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182650Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192650Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202650Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212650Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222650Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232650Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242650Ssaidi@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252650Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262650Ssaidi@eecs.umich.edu# 272665Ssaidi@eecs.umich.edu# Authors: Lisa Hsu 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu# system options 302650Ssaidi@eecs.umich.eduparser.add_option("-d", "--detailed", action="store_true") 312650Ssaidi@eecs.umich.eduparser.add_option("-t", "--timing", action="store_true") 322650Ssaidi@eecs.umich.eduparser.add_option("-n", "--num_cpus", type="int", default=1) 332650Ssaidi@eecs.umich.eduparser.add_option("--caches", action="store_true") 342650Ssaidi@eecs.umich.edu 352650Ssaidi@eecs.umich.edu# Run duration options 363804Ssaidi@eecs.umich.eduparser.add_option("-m", "--maxtick", type="int") 372650Ssaidi@eecs.umich.eduparser.add_option("--maxtime", type="float") 382680Sktlim@umich.edu 392650Ssaidi@eecs.umich.edu# Checkpointing options 402650Ssaidi@eecs.umich.edu###Note that performing checkpointing via python script files will override 412650Ssaidi@eecs.umich.edu###checkpoint instructions built into binaries. 422650Ssaidi@eecs.umich.eduparser.add_option("--take_checkpoints", action="store", type="string", 432650Ssaidi@eecs.umich.edu help="<M,N> will take checkpoint at cycle M and every N cycles \ 442650Ssaidi@eecs.umich.edu thereafter") 452650Ssaidi@eecs.umich.eduparser.add_option("--max_checkpoints", action="store", type="int", 462650Ssaidi@eecs.umich.edu help="the maximum number of checkpoints to drop", 472680Sktlim@umich.edu default=5) 482650Ssaidi@eecs.umich.eduparser.add_option("--checkpoint_dir", action="store", type="string", 492680Sktlim@umich.edu help="Place all checkpoints in this absolute directory") 502680Sktlim@umich.eduparser.add_option("-r", "--checkpoint_restore", action="store", type="int", 512680Sktlim@umich.edu help="restore from checkpoint <N>") 522680Sktlim@umich.edu 532650Ssaidi@eecs.umich.edu# CPU Switching - default switch model goes from a checkpoint 542650Ssaidi@eecs.umich.edu# to a timing simple CPU with caches to warm up, then to detailed CPU for 552650Ssaidi@eecs.umich.edu# data measurement 562650Ssaidi@eecs.umich.eduparser.add_option("-s", "--standard_switch", action="store_true", 57 help="switch from one cpu mode to another") 58