MemConfig.py revision 10675:bb7cd7193edc 
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35#
36# Authors: Andreas Sandberg
37#          Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42from textwrap import  TextWrapper
43
44# Dictionary of mapping names of real memory controller models to
45# classes.
46_mem_classes = {}
47
48# Memory aliases. We make sure they exist before we add them to the
49# fina; list. A target may be specified as a tuple, in which case the
50# first available memory controller model in the tuple will be used.
51_mem_aliases_all = [
52    ("simple_mem", "SimpleMemory"),
53    ("ddr3_1600_x64", "DDR3_1600_x64"),
54    ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
55    ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
56    ("wio_200_x128", "WideIO_200_x128"),
57    ("dramsim2", "DRAMSim2"),
58    ("ruby_memory", "RubyMemoryControl")
59    ]
60
61# Filtered list of aliases. Only aliases for existing memory
62# controllers exist in this list.
63_mem_aliases = {}
64
65
66def is_mem_class(cls):
67    """Determine if a class is a memory controller that can be instantiated"""
68
69    # We can't use the normal inspect.isclass because the ParamFactory
70    # and ProxyFactory classes have a tendency to confuse it.
71    try:
72        return issubclass(cls, m5.objects.AbstractMemory) and \
73            not cls.abstract
74    except TypeError:
75        return False
76
77def get(name):
78    """Get a memory class from a user provided class name or alias."""
79
80    real_name = _mem_aliases.get(name, name)
81
82    try:
83        mem_class = _mem_classes[real_name]
84        return mem_class
85    except KeyError:
86        print "%s is not a valid memory controller." % (name,)
87        sys.exit(1)
88
89def print_mem_list():
90    """Print a list of available memory classes including their aliases."""
91
92    print "Available memory classes:"
93    doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
94    for name, cls in _mem_classes.items():
95        print "\t%s" % name
96
97        # Try to extract the class documentation from the class help
98        # string.
99        doc = inspect.getdoc(cls)
100        if doc:
101            for line in doc_wrapper.wrap(doc):
102                print line
103
104    if _mem_aliases:
105        print "\nMemory aliases:"
106        for alias, target in _mem_aliases.items():
107            print "\t%s => %s" % (alias, target)
108
109def mem_names():
110    """Return a list of valid memory names."""
111    return _mem_classes.keys() + _mem_aliases.keys()
112
113# Add all memory controllers in the object hierarchy.
114for name, cls in inspect.getmembers(m5.objects, is_mem_class):
115    _mem_classes[name] = cls
116
117for alias, target in _mem_aliases_all:
118    if isinstance(target, tuple):
119        # Some aliases contain a list of memory controller models
120        # sorted in priority order. Use the first target that's
121        # available.
122        for t in target:
123            if t in _mem_classes:
124                _mem_aliases[alias] = t
125                break
126    elif target in _mem_classes:
127        # Normal alias
128        _mem_aliases[alias] = target
129
130def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
131    """
132    Helper function for creating a single memoy controller from the given
133    options.  This function is invoked multiple times in config_mem function
134    to create an array of controllers.
135    """
136
137    import math
138    intlv_low_bit = int(math.log(intlv_size, 2))
139
140    # Create an instance so we can figure out the address
141    # mapping and row-buffer size
142    ctrl = cls()
143
144    # Only do this for DRAMs
145    if issubclass(cls, m5.objects.DRAMCtrl):
146        # Inform each controller how many channels to account
147        # for
148        ctrl.channels = nbr_mem_ctrls
149
150        # If the channel bits are appearing after the column
151        # bits, we need to add the appropriate number of bits
152        # for the row buffer size
153        if ctrl.addr_mapping.value == 'RoRaBaChCo':
154            # This computation only really needs to happen
155            # once, but as we rely on having an instance we
156            # end up having to repeat it for each and every
157            # one
158            rowbuffer_size = ctrl.device_rowbuffer_size.value * \
159                ctrl.devices_per_rank.value
160
161            intlv_low_bit = int(math.log(rowbuffer_size, 2))
162
163    # We got all we need to configure the appropriate address
164    # range
165    ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
166                                      intlvHighBit = \
167                                          intlv_low_bit + intlv_bits - 1,
168                                      intlvBits = intlv_bits,
169                                      intlvMatch = i)
170    return ctrl
171
172def config_mem(options, system):
173    """
174    Create the memory controllers based on the options and attach them.
175
176    If requested, we make a multi-channel configuration of the
177    selected memory controller class by creating multiple instances of
178    the specific class. The individual controllers have their
179    parameters set such that the address range is interleaved between
180    them.
181    """
182
183    nbr_mem_ctrls = options.mem_channels
184    import math
185    from m5.util import fatal
186    intlv_bits = int(math.log(nbr_mem_ctrls, 2))
187    if 2 ** intlv_bits != nbr_mem_ctrls:
188        fatal("Number of memory channels must be a power of 2")
189
190    cls = get(options.mem_type)
191    mem_ctrls = []
192
193    # The default behaviour is to interleave memory channels on 128
194    # byte granularity, or cache line granularity if larger than 128
195    # byte. This value is based on the locality seen across a large
196    # range of workloads.
197    intlv_size = max(128, system.cache_line_size.value)
198
199    # For every range (most systems will only have one), create an
200    # array of controllers and set their parameters to match their
201    # address mapping in the case of a DRAM
202    for r in system.mem_ranges:
203        for i in xrange(nbr_mem_ctrls):
204            mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
205                                       intlv_size)
206            # Set the number of ranks based on the command-line
207            # options if it was explicitly set
208            if issubclass(cls, m5.objects.DRAMCtrl) and \
209                    options.mem_ranks:
210                mem_ctrl.ranks_per_channel = options.mem_ranks
211
212            mem_ctrls.append(mem_ctrl)
213
214    system.mem_ctrls = mem_ctrls
215
216    # Connect the controllers to the membus
217    for i in xrange(len(system.mem_ctrls)):
218        system.mem_ctrls[i].port = system.membus.master
219