GPUTLBConfig.py revision 12647
110037SARM gem5 Developers# Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# For use for simulation and test purposes only 57090SN/A# 67090SN/A# Redistribution and use in source and binary forms, with or without 77090SN/A# modification, are permitted provided that the following conditions are met: 87090SN/A# 97090SN/A# 1. Redistributions of source code must retain the above copyright notice, 107090SN/A# this list of conditions and the following disclaimer. 117090SN/A# 127090SN/A# 2. Redistributions in binary form must reproduce the above copyright notice, 134486SN/A# this list of conditions and the following disclaimer in the documentation 144486SN/A# and/or other materials provided with the distribution. 154486SN/A# 164486SN/A# 3. Neither the name of the copyright holder nor the names of its 174486SN/A# contributors may be used to endorse or promote products derived from this 184486SN/A# software without specific prior written permission. 194486SN/A# 204486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 214486SN/A# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 224486SN/A# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 234486SN/A# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 244486SN/A# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 254486SN/A# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 264486SN/A# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 274486SN/A# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 284486SN/A# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 294486SN/A# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 304486SN/A# POSSIBILITY OF SUCH DAMAGE. 314486SN/A# 324486SN/A# Authors: Lisa Hsu 334486SN/A 344486SN/Afrom __future__ import print_function 354486SN/A 364486SN/A# Configure the TLB hierarchy 374486SN/A# Places which would probably need to be modified if you 384486SN/A# want a different hierarchy are specified by a <Modify here .. >' 397584SAli.Saidi@arm.com# comment 407584SAli.Saidi@arm.comimport m5 417754SWilliam.Wang@arm.comfrom m5.objects import * 424486SN/A 433630SN/Adef TLB_constructor(level): 443630SN/A 457587SAli.Saidi@arm.com constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries, \ 468525SAli.Saidi@ARM.com assoc = options.L%(level)dTLBassoc, \ 478525SAli.Saidi@ARM.com hitLatency = options.L%(level)dAccessLatency,\ 488212SAli.Saidi@ARM.com missLatency2 = options.L%(level)dMissLatency,\ 495478SN/A maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\ 505478SN/A accessDistance = options.L%(level)dAccessDistanceStat,\ 517584SAli.Saidi@arm.com clk_domain = SrcClockDomain(\ 528931Sandreas.hansson@arm.com clock = options.GPUClock,\ 539525SAndreas.Sandberg@ARM.com voltage_domain = VoltageDomain(\ 543630SN/A voltage = options.gpu_voltage)))" % locals() 559806Sstever@gmail.com return constructor_call 569806Sstever@gmail.com 577584SAli.Saidi@arm.comdef Coalescer_constructor(level): 589338SAndreas.Sandberg@arm.com 597584SAli.Saidi@arm.com constructor_call = "TLBCoalescer(probesPerCycle = \ 603898SN/A options.L%(level)dProbesPerCycle, \ 619806Sstever@gmail.com coalescingWindow = options.L%(level)dCoalescingWindow,\ 627950SAli.Saidi@ARM.com disableCoalescing = options.L%(level)dDisableCoalescing,\ 637950SAli.Saidi@ARM.com clk_domain = SrcClockDomain(\ 649338SAndreas.Sandberg@arm.com clock = options.GPUClock,\ 659525SAndreas.Sandberg@ARM.com voltage_domain = VoltageDomain(\ 667950SAli.Saidi@ARM.com voltage = options.gpu_voltage)))" % locals() 677950SAli.Saidi@ARM.com return constructor_call 687950SAli.Saidi@ARM.com 697950SAli.Saidi@ARM.comdef create_TLB_Coalescer(options, my_level, my_index, TLB_name, Coalescer_name): 707587SAli.Saidi@arm.com # arguments: options, TLB level, number of private structures for this Level, 717587SAli.Saidi@arm.com # TLB name and Coalescer name 727587SAli.Saidi@arm.com for i in xrange(my_index): 739338SAndreas.Sandberg@arm.com TLB_name.append(eval(TLB_constructor(my_level))) 747753SWilliam.Wang@arm.com Coalescer_name.append(eval(Coalescer_constructor(my_level))) 757753SWilliam.Wang@arm.com 769525SAndreas.Sandberg@ARM.comdef config_tlb_hierarchy(options, system, shader_idx): 777753SWilliam.Wang@arm.com n_cu = options.num_compute_units 787587SAli.Saidi@arm.com # Make this configurable now, instead of the hard coded val. The dispatcher 797587SAli.Saidi@arm.com # is always the last item in the system.cpu list. 808282SAli.Saidi@ARM.com dispatcher_idx = len(system.cpu) - 1 818282SAli.Saidi@ARM.com 829338SAndreas.Sandberg@arm.com if options.TLB_config == "perLane": 838282SAli.Saidi@ARM.com num_TLBs = 64 * n_cu 847584SAli.Saidi@arm.com elif options.TLB_config == "mono": 857584SAli.Saidi@arm.com num_TLBs = 1 869338SAndreas.Sandberg@arm.com elif options.TLB_config == "perCU": 878524SAli.Saidi@ARM.com num_TLBs = n_cu 888524SAli.Saidi@ARM.com elif options.TLB_config == "2CU": 898299Schander.sudanthi@arm.com num_TLBs = n_cu >> 1 907584SAli.Saidi@arm.com else: 9110037SARM gem5 Developers print("Bad option for TLB Configuration.") 9210037SARM gem5 Developers sys.exit(1) 9310037SARM gem5 Developers 9410037SARM gem5 Developers #---------------------------------------------------------------------------------------- 9510037SARM gem5 Developers # A visual representation of the TLB hierarchy 9610037SARM gem5 Developers # for ease of configuration 9710037SARM gem5 Developers # < Modify here the width and the number of levels if you want a different configuration > 9810037SARM gem5 Developers # width is the number of TLBs of the given type (i.e., D-TLB, I-TLB etc) for this level 9910037SARM gem5 Developers L1 = [{'name': 'sqc', 'width': options.num_sqc, 'TLBarray': [], 'CoalescerArray': []}, 10010037SARM gem5 Developers {'name': 'dispatcher', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}, 10110037SARM gem5 Developers {'name': 'l1', 'width': num_TLBs, 'TLBarray': [], 'CoalescerArray': []}] 1029806Sstever@gmail.com 1037584SAli.Saidi@arm.com L2 = [{'name': 'l2', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}] 1049338SAndreas.Sandberg@arm.com L3 = [{'name': 'l3', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}] 1057584SAli.Saidi@arm.com 1067584SAli.Saidi@arm.com TLB_hierarchy = [L1, L2, L3] 1077584SAli.Saidi@arm.com 1087584SAli.Saidi@arm.com #---------------------------------------------------------------------------------------- 1097584SAli.Saidi@arm.com # Create the hiearchy 1109338SAndreas.Sandberg@arm.com # Call the appropriate constructors and add objects to the system 1119525SAndreas.Sandberg@ARM.com 1127584SAli.Saidi@arm.com for i in xrange(len(TLB_hierarchy)): 1137584SAli.Saidi@arm.com hierarchy_level = TLB_hierarchy[i] 1147584SAli.Saidi@arm.com level = i+1 1157584SAli.Saidi@arm.com for TLB_type in hierarchy_level: 1169806Sstever@gmail.com TLB_index = TLB_type['width'] 1177584SAli.Saidi@arm.com TLB_array = TLB_type['TLBarray'] 1189338SAndreas.Sandberg@arm.com Coalescer_array = TLB_type['CoalescerArray'] 1199525SAndreas.Sandberg@ARM.com # If the sim calls for a fixed L1 TLB size across CUs, 1207584SAli.Saidi@arm.com # override the TLB entries option 1217584SAli.Saidi@arm.com if options.tot_L1TLB_size: 1227584SAli.Saidi@arm.com options.L1TLBentries = options.tot_L1TLB_size / num_TLBs 1237584SAli.Saidi@arm.com if options.L1TLBassoc > options.L1TLBentries: 1247584SAli.Saidi@arm.com options.L1TLBassoc = options.L1TLBentries 1257584SAli.Saidi@arm.com # call the constructors for the TLB and the Coalescer 1268512Sgeoffrey.blake@arm.com create_TLB_Coalescer(options, level, TLB_index,\ 1278512Sgeoffrey.blake@arm.com TLB_array, Coalescer_array) 1289338SAndreas.Sandberg@arm.com 1299525SAndreas.Sandberg@ARM.com system_TLB_name = TLB_type['name'] + '_tlb' 1308512Sgeoffrey.blake@arm.com system_Coalescer_name = TLB_type['name'] + '_coalescer' 1318512Sgeoffrey.blake@arm.com 1328512Sgeoffrey.blake@arm.com # add the different TLB levels to the system 13310037SARM gem5 Developers # Modify here if you want to make the TLB hierarchy a child of 13410037SARM gem5 Developers # the shader. 13510037SARM gem5 Developers exec('system.%s = TLB_array' % system_TLB_name) 13610037SARM gem5 Developers exec('system.%s = Coalescer_array' % system_Coalescer_name) 13710037SARM gem5 Developers 13810037SARM gem5 Developers #=========================================================== 13910037SARM gem5 Developers # Specify the TLB hierarchy (i.e., port connections) 14010037SARM gem5 Developers # All TLBs but the last level TLB need to have a memSidePort (master) 14110037SARM gem5 Developers #=========================================================== 1428870SAli.Saidi@ARM.com 1438870SAli.Saidi@ARM.com # Each TLB is connected with its Coalescer through a single port. 1449338SAndreas.Sandberg@arm.com # There is a one-to-one mapping of TLBs to Coalescers at a given level 1458870SAli.Saidi@ARM.com # This won't be modified no matter what the hierarchy looks like. 1468870SAli.Saidi@ARM.com for i in xrange(len(TLB_hierarchy)): 1478870SAli.Saidi@ARM.com hierarchy_level = TLB_hierarchy[i] 1487950SAli.Saidi@ARM.com level = i+1 1497754SWilliam.Wang@arm.com for TLB_type in hierarchy_level: 1509338SAndreas.Sandberg@arm.com name = TLB_type['name'] 1519330Schander.sudanthi@arm.com for index in range(TLB_type['width']): 1527950SAli.Saidi@ARM.com exec('system.%s_coalescer[%d].master[0] = \ 1537950SAli.Saidi@ARM.com system.%s_tlb[%d].slave[0]' % \ 1547754SWilliam.Wang@arm.com (name, index, name, index)) 1557754SWilliam.Wang@arm.com 1567753SWilliam.Wang@arm.com # Connect the cpuSidePort (slave) of all the coalescers in level 1 1577753SWilliam.Wang@arm.com # < Modify here if you want a different configuration > 1589338SAndreas.Sandberg@arm.com for TLB_type in L1: 1599394Sandreas.hansson@arm.com name = TLB_type['name'] 1609330Schander.sudanthi@arm.com num_TLBs = TLB_type['width'] 1617753SWilliam.Wang@arm.com if name == 'l1': # L1 D-TLBs 1629939Sdam.sunwoo@arm.com tlb_per_cu = num_TLBs / n_cu 1639939Sdam.sunwoo@arm.com for cu_idx in range(n_cu): 1647753SWilliam.Wang@arm.com if tlb_per_cu: 1659646SChris.Emmons@arm.com for tlb in range(tlb_per_cu): 1669646SChris.Emmons@arm.com exec('system.cpu[%d].CUs[%d].translation_port[%d] = \ 1679646SChris.Emmons@arm.com system.l1_coalescer[%d].slave[%d]' % \ 16810187SChris.Emmons@arm.com (shader_idx, cu_idx, tlb, cu_idx*tlb_per_cu+tlb, 0)) 16910187SChris.Emmons@arm.com else: 17010187SChris.Emmons@arm.com exec('system.cpu[%d].CUs[%d].translation_port[%d] = \ 17110187SChris.Emmons@arm.com system.l1_coalescer[%d].slave[%d]' % \ 17210187SChris.Emmons@arm.com (shader_idx, cu_idx, tlb_per_cu, cu_idx / (n_cu / num_TLBs), cu_idx % (n_cu / num_TLBs))) 17310187SChris.Emmons@arm.com 1749646SChris.Emmons@arm.com elif name == 'dispatcher': # Dispatcher TLB 1759646SChris.Emmons@arm.com for index in range(TLB_type['width']): 1769646SChris.Emmons@arm.com exec('system.cpu[%d].translation_port = \ 1779939Sdam.sunwoo@arm.com system.dispatcher_coalescer[%d].slave[0]' % \ 1789646SChris.Emmons@arm.com (dispatcher_idx, index)) 1797584SAli.Saidi@arm.com elif name == 'sqc': # I-TLB 1807584SAli.Saidi@arm.com for index in range(n_cu): 1819338SAndreas.Sandberg@arm.com sqc_tlb_index = index / options.cu_per_sqc 1823630SN/A sqc_tlb_port_id = index % options.cu_per_sqc 1838525SAli.Saidi@ARM.com exec('system.cpu[%d].CUs[%d].sqc_tlb_port = \ 1848870SAli.Saidi@ARM.com system.sqc_coalescer[%d].slave[%d]' % \ 1858870SAli.Saidi@ARM.com (shader_idx, index, sqc_tlb_index, sqc_tlb_port_id)) 1868870SAli.Saidi@ARM.com 1878870SAli.Saidi@ARM.com 1889835Sandreas.hansson@arm.com # Connect the memSidePorts (masters) of all the TLBs with the 1899835Sandreas.hansson@arm.com # cpuSidePorts (slaves) of the Coalescers of the next level 1908870SAli.Saidi@ARM.com # < Modify here if you want a different configuration > 1918870SAli.Saidi@ARM.com # L1 <-> L2 19210037SARM gem5 Developers l2_coalescer_index = 0 19310037SARM gem5 Developers for TLB_type in L1: 19410037SARM gem5 Developers name = TLB_type['name'] 1958870SAli.Saidi@ARM.com for index in range(TLB_type['width']): 1963630SN/A exec('system.%s_tlb[%d].master[0] = \ 1977753SWilliam.Wang@arm.com system.l2_coalescer[0].slave[%d]' % \ 1987753SWilliam.Wang@arm.com (name, index, l2_coalescer_index)) 1997753SWilliam.Wang@arm.com l2_coalescer_index += 1 2007584SAli.Saidi@arm.com # L2 <-> L3 2017584SAli.Saidi@arm.com system.l2_tlb[0].master[0] = system.l3_coalescer[0].slave[0] 2027584SAli.Saidi@arm.com 2039525SAndreas.Sandberg@ARM.com return system 2047584SAli.Saidi@arm.com