FSConfig.py revision 9539:0ac00d9a8aaf 
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59    IO_address_space_base = 0x80000000000
60    class BaseTsunami(Tsunami):
61        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63                            pci_func=0, pci_dev=0, pci_bus=0)
64
65    self = LinuxAlphaSystem()
66    if not mdesc:
67        # generic system
68        mdesc = SysConfig()
69    self.readfile = mdesc.script()
70    self.iobus = NoncoherentBus()
71    self.membus = MemBus()
72    # By default the bridge responds to all addresses above the I/O
73    # base address (including the PCI config space)
74    self.bridge = Bridge(delay='50ns',
75                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
76    self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
77    self.mem_ranges = [self.physmem.range]
78    self.bridge.master = self.iobus.slave
79    self.bridge.slave = self.membus.master
80    self.physmem.port = self.membus.master
81    self.disk0 = CowIdeDisk(driveID='master')
82    self.disk2 = CowIdeDisk(driveID='master')
83    self.disk0.childImage(mdesc.disk())
84    self.disk2.childImage(disk('linux-bigswap2.img'))
85    self.tsunami = BaseTsunami()
86    self.tsunami.attachIO(self.iobus)
87    self.tsunami.ide.pio = self.iobus.master
88    self.tsunami.ide.config = self.iobus.master
89    self.tsunami.ide.dma = self.iobus.slave
90    self.tsunami.ethernet.pio = self.iobus.master
91    self.tsunami.ethernet.config = self.iobus.master
92    self.tsunami.ethernet.dma = self.iobus.slave
93    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
94                                               read_only = True))
95    self.intrctrl = IntrControl()
96    self.mem_mode = mem_mode
97    self.terminal = Terminal()
98    self.kernel = binary('vmlinux')
99    self.pal = binary('ts_osfpal')
100    self.console = binary('console')
101    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
102
103    self.system_port = self.membus.slave
104
105    return self
106
107def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
108    class BaseTsunami(Tsunami):
109        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
110        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
111                            pci_func=0, pci_dev=0, pci_bus=0)
112
113    physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
114    self = LinuxAlphaSystem(physmem = physmem)
115    self.mem_ranges = [self.physmem.range]
116    if not mdesc:
117        # generic system
118        mdesc = SysConfig()
119    self.readfile = mdesc.script()
120
121    # Create pio bus to connect all device pio ports to rubymem's pio port
122    self.piobus = NoncoherentBus()
123
124    #
125    # Pio functional accesses from devices need direct access to memory
126    # RubyPort currently does support functional accesses.  Therefore provide
127    # the piobus a direct connection to physical memory
128    #
129    self.piobus.master = physmem.port
130
131    self.disk0 = CowIdeDisk(driveID='master')
132    self.disk2 = CowIdeDisk(driveID='master')
133    self.disk0.childImage(mdesc.disk())
134    self.disk2.childImage(disk('linux-bigswap2.img'))
135    self.tsunami = BaseTsunami()
136    self.tsunami.attachIO(self.piobus)
137    self.tsunami.ide.pio = self.piobus.master
138    self.tsunami.ide.config = self.piobus.master
139    self.tsunami.ethernet.pio = self.piobus.master
140    self.tsunami.ethernet.config = self.piobus.master
141
142    #
143    # Store the dma devices for later connection to dma ruby ports.
144    # Append an underscore to dma_devices to avoid the SimObjectVector check.
145    #
146    self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
147
148    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
149                                               read_only = True))
150    self.intrctrl = IntrControl()
151    self.mem_mode = mem_mode
152    self.terminal = Terminal()
153    self.kernel = binary('vmlinux')
154    self.pal = binary('ts_osfpal')
155    self.console = binary('console')
156    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
157
158    return self
159
160def makeSparcSystem(mem_mode, mdesc = None):
161    # Constants from iob.cc and uart8250.cc
162    iob_man_addr = 0x9800000000
163    uart_pio_size = 8
164
165    class CowMmDisk(MmDisk):
166        image = CowDiskImage(child=RawDiskImage(read_only=True),
167                             read_only=False)
168
169        def childImage(self, ci):
170            self.image.child.image_file = ci
171
172    self = SparcSystem()
173    if not mdesc:
174        # generic system
175        mdesc = SysConfig()
176    self.readfile = mdesc.script()
177    self.iobus = NoncoherentBus()
178    self.membus = MemBus()
179    self.bridge = Bridge(delay='50ns')
180    self.t1000 = T1000()
181    self.t1000.attachOnChipIO(self.membus)
182    self.t1000.attachIO(self.iobus)
183    self.physmem = SimpleDDR3(range = AddrRange(Addr('1MB'), size = '64MB'),
184                              zero = True)
185    self.physmem2 = SimpleDDR3(range = AddrRange(Addr('2GB'), size ='256MB'),
186                               zero = True)
187    self.mem_ranges = [self.physmem.range, self.physmem2.range]
188    self.bridge.master = self.iobus.slave
189    self.bridge.slave = self.membus.master
190    self.physmem.port = self.membus.master
191    self.physmem2.port = self.membus.master
192    self.rom.port = self.membus.master
193    self.nvram.port = self.membus.master
194    self.hypervisor_desc.port = self.membus.master
195    self.partition_desc.port = self.membus.master
196    self.intrctrl = IntrControl()
197    self.disk0 = CowMmDisk()
198    self.disk0.childImage(disk('disk.s10hw2'))
199    self.disk0.pio = self.iobus.master
200
201    # The puart0 and hvuart are placed on the IO bus, so create ranges
202    # for them. The remaining IO range is rather fragmented, so poke
203    # holes for the iob and partition descriptors etc.
204    self.bridge.ranges = \
205        [
206        AddrRange(self.t1000.puart0.pio_addr,
207                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
208        AddrRange(self.disk0.pio_addr,
209                  self.t1000.fake_jbi.pio_addr +
210                  self.t1000.fake_jbi.pio_size - 1),
211        AddrRange(self.t1000.fake_clk.pio_addr,
212                  iob_man_addr - 1),
213        AddrRange(self.t1000.fake_l2_1.pio_addr,
214                  self.t1000.fake_ssi.pio_addr +
215                  self.t1000.fake_ssi.pio_size - 1),
216        AddrRange(self.t1000.hvuart.pio_addr,
217                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
218        ]
219    self.reset_bin = binary('reset_new.bin')
220    self.hypervisor_bin = binary('q_new.bin')
221    self.openboot_bin = binary('openboot_new.bin')
222    self.nvram_bin = binary('nvram1')
223    self.hypervisor_desc_bin = binary('1up-hv.bin')
224    self.partition_desc_bin = binary('1up-md.bin')
225
226    self.system_port = self.membus.slave
227
228    return self
229
230def makeArmSystem(mem_mode, machine_type, mdesc = None, dtb_filename = None,
231                  bare_metal=False):
232    assert machine_type
233
234    if bare_metal:
235        self = ArmSystem()
236    else:
237        self = LinuxArmSystem()
238
239    if not mdesc:
240        # generic system
241        mdesc = SysConfig()
242
243    self.readfile = mdesc.script()
244    self.iobus = NoncoherentBus()
245    self.membus = MemBus()
246    self.membus.badaddr_responder.warn_access = "warn"
247    self.bridge = Bridge(delay='50ns')
248    self.bridge.master = self.iobus.slave
249    self.bridge.slave = self.membus.master
250
251    self.mem_mode = mem_mode
252
253    if machine_type == "RealView_PBX":
254        self.realview = RealViewPBX()
255    elif machine_type == "RealView_EB":
256        self.realview = RealViewEB()
257    elif machine_type == "VExpress_ELT":
258        self.realview = VExpress_ELT()
259    elif machine_type == "VExpress_EMM":
260        self.realview = VExpress_EMM()
261        self.load_addr_mask = 0xffffffff
262    else:
263        print "Unknown Machine Type"
264        sys.exit(1)
265
266    self.cf0 = CowIdeDisk(driveID='master')
267    self.cf0.childImage(mdesc.disk())
268    # default to an IDE controller rather than a CF one
269    # assuming we've got one
270    try:
271        self.realview.ide.disks = [self.cf0]
272    except:
273        self.realview.cf_ctrl.disks = [self.cf0]
274
275    if bare_metal:
276        # EOT character on UART will end the simulation
277        self.realview.uart.end_on_eot = True
278        self.physmem = SimpleDDR3(range = AddrRange(Addr(mdesc.mem())),
279                                  zero = True)
280        self.mem_ranges = [self.physmem.range]
281    else:
282        self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
283        if dtb_filename is not None:
284            self.dtb_filename = dtb_filename
285        self.machine_type = machine_type
286        if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
287            print "The currently selected ARM platforms doesn't support"
288            print " the amount of DRAM you've selected. Please try"
289            print " another platform"
290            sys.exit(1)
291
292        boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
293                     'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
294
295        self.physmem = SimpleDDR3(range =
296                                  AddrRange(self.realview.mem_start_addr,
297                                            size = mdesc.mem()),
298                                  conf_table_reported = True)
299        self.mem_ranges = [self.physmem.range]
300        self.realview.setupBootLoader(self.membus, self, binary)
301        self.gic_cpu_addr = self.realview.gic.cpu_addr
302        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
303
304        if mdesc.disk().lower().count('android'):
305            boot_flags += " init=/init "
306        self.boot_osflags = boot_flags
307
308    self.physmem.port = self.membus.master
309    self.realview.attachOnChipIO(self.membus, self.bridge)
310    self.realview.attachIO(self.iobus)
311    self.intrctrl = IntrControl()
312    self.terminal = Terminal()
313    self.vncserver = VncServer()
314
315    self.system_port = self.membus.slave
316
317    return self
318
319
320def makeLinuxMipsSystem(mem_mode, mdesc = None):
321    class BaseMalta(Malta):
322        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
323        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
324                            pci_func=0, pci_dev=0, pci_bus=0)
325
326    self = LinuxMipsSystem()
327    if not mdesc:
328        # generic system
329        mdesc = SysConfig()
330    self.readfile = mdesc.script()
331    self.iobus = NoncoherentBus()
332    self.membus = MemBus()
333    self.bridge = Bridge(delay='50ns')
334    self.physmem = SimpleDDR3(range = AddrRange('1GB'))
335    self.mem_ranges = [self.physmem.range]
336    self.bridge.master = self.iobus.slave
337    self.bridge.slave = self.membus.master
338    self.physmem.port = self.membus.master
339    self.disk0 = CowIdeDisk(driveID='master')
340    self.disk2 = CowIdeDisk(driveID='master')
341    self.disk0.childImage(mdesc.disk())
342    self.disk2.childImage(disk('linux-bigswap2.img'))
343    self.malta = BaseMalta()
344    self.malta.attachIO(self.iobus)
345    self.malta.ide.pio = self.iobus.master
346    self.malta.ide.config = self.iobus.master
347    self.malta.ide.dma = self.iobus.slave
348    self.malta.ethernet.pio = self.iobus.master
349    self.malta.ethernet.config = self.iobus.master
350    self.malta.ethernet.dma = self.iobus.slave
351    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
352                                               read_only = True))
353    self.intrctrl = IntrControl()
354    self.mem_mode = mem_mode
355    self.terminal = Terminal()
356    self.kernel = binary('mips/vmlinux')
357    self.console = binary('mips/console')
358    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
359
360    self.system_port = self.membus.slave
361
362    return self
363
364def x86IOAddress(port):
365    IO_address_space_base = 0x8000000000000000
366    return IO_address_space_base + port
367
368def connectX86ClassicSystem(x86_sys, numCPUs):
369    # Constants similar to x86_traits.hh
370    IO_address_space_base = 0x8000000000000000
371    pci_config_address_space_base = 0xc000000000000000
372    interrupts_address_space_base = 0xa000000000000000
373    APIC_range_size = 1 << 12;
374
375    x86_sys.membus = MemBus()
376    x86_sys.physmem.port = x86_sys.membus.master
377
378    # North Bridge
379    x86_sys.iobus = NoncoherentBus()
380    x86_sys.bridge = Bridge(delay='50ns')
381    x86_sys.bridge.master = x86_sys.iobus.slave
382    x86_sys.bridge.slave = x86_sys.membus.master
383    # Allow the bridge to pass through the IO APIC (two pages),
384    # everything in the IO address range up to the local APIC, and
385    # then the entire PCI address space and beyond
386    x86_sys.bridge.ranges = \
387        [
388        AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
389                  x86_sys.pc.south_bridge.io_apic.pio_addr +
390                  APIC_range_size - 1),
391        AddrRange(IO_address_space_base,
392                  interrupts_address_space_base - 1),
393        AddrRange(pci_config_address_space_base,
394                  Addr.max)
395        ]
396
397    # Create a bridge from the IO bus to the memory bus to allow access to
398    # the local APIC (two pages)
399    x86_sys.apicbridge = Bridge(delay='50ns')
400    x86_sys.apicbridge.slave = x86_sys.iobus.master
401    x86_sys.apicbridge.master = x86_sys.membus.slave
402    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
403                                           interrupts_address_space_base +
404                                           numCPUs * APIC_range_size
405                                           - 1)]
406
407    # connect the io bus
408    x86_sys.pc.attachIO(x86_sys.iobus)
409
410    x86_sys.system_port = x86_sys.membus.slave
411
412def connectX86RubySystem(x86_sys):
413    # North Bridge
414    x86_sys.piobus = NoncoherentBus()
415
416    #
417    # Pio functional accesses from devices need direct access to memory
418    # RubyPort currently does support functional accesses.  Therefore provide
419    # the piobus a direct connection to physical memory
420    #
421    x86_sys.piobus.master = x86_sys.physmem.port
422    # add the ide to the list of dma devices that later need to attach to
423    # dma controllers
424    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
425    x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
426
427
428def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
429    if self == None:
430        self = X86System()
431
432    if not mdesc:
433        # generic system
434        mdesc = SysConfig()
435    self.readfile = mdesc.script()
436
437    self.mem_mode = mem_mode
438
439    # Physical memory
440    self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
441    self.mem_ranges = [self.physmem.range]
442
443    # Platform
444    self.pc = Pc()
445
446    # Create and connect the busses required by each memory system
447    if Ruby:
448        connectX86RubySystem(self)
449    else:
450        connectX86ClassicSystem(self, numCPUs)
451
452    self.intrctrl = IntrControl()
453
454    # Disks
455    disk0 = CowIdeDisk(driveID='master')
456    disk2 = CowIdeDisk(driveID='master')
457    disk0.childImage(mdesc.disk())
458    disk2.childImage(disk('linux-bigswap2.img'))
459    self.pc.south_bridge.ide.disks = [disk0, disk2]
460
461    # Add in a Bios information structure.
462    structures = [X86SMBiosBiosInformation()]
463    self.smbios_table.structures = structures
464
465    # Set up the Intel MP table
466    base_entries = []
467    ext_entries = []
468    for i in xrange(numCPUs):
469        bp = X86IntelMPProcessor(
470                local_apic_id = i,
471                local_apic_version = 0x14,
472                enable = True,
473                bootstrap = (i == 0))
474        base_entries.append(bp)
475    io_apic = X86IntelMPIOAPIC(
476            id = numCPUs,
477            version = 0x11,
478            enable = True,
479            address = 0xfec00000)
480    self.pc.south_bridge.io_apic.apic_id = io_apic.id
481    base_entries.append(io_apic)
482    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
483    base_entries.append(isa_bus)
484    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
485    base_entries.append(pci_bus)
486    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
487            subtractive_decode=True, parent_bus=1)
488    ext_entries.append(connect_busses)
489    pci_dev4_inta = X86IntelMPIOIntAssignment(
490            interrupt_type = 'INT',
491            polarity = 'ConformPolarity',
492            trigger = 'ConformTrigger',
493            source_bus_id = 1,
494            source_bus_irq = 0 + (4 << 2),
495            dest_io_apic_id = io_apic.id,
496            dest_io_apic_intin = 16)
497    base_entries.append(pci_dev4_inta)
498    def assignISAInt(irq, apicPin):
499        assign_8259_to_apic = X86IntelMPIOIntAssignment(
500                interrupt_type = 'ExtInt',
501                polarity = 'ConformPolarity',
502                trigger = 'ConformTrigger',
503                source_bus_id = 0,
504                source_bus_irq = irq,
505                dest_io_apic_id = io_apic.id,
506                dest_io_apic_intin = 0)
507        base_entries.append(assign_8259_to_apic)
508        assign_to_apic = X86IntelMPIOIntAssignment(
509                interrupt_type = 'INT',
510                polarity = 'ConformPolarity',
511                trigger = 'ConformTrigger',
512                source_bus_id = 0,
513                source_bus_irq = irq,
514                dest_io_apic_id = io_apic.id,
515                dest_io_apic_intin = apicPin)
516        base_entries.append(assign_to_apic)
517    assignISAInt(0, 2)
518    assignISAInt(1, 1)
519    for i in range(3, 15):
520        assignISAInt(i, i)
521    self.intel_mp_table.base_entries = base_entries
522    self.intel_mp_table.ext_entries = ext_entries
523
524def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
525    self = LinuxX86System()
526
527    # Build up the x86 system and then specialize it for Linux
528    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
529
530    # We assume below that there's at least 1MB of memory. We'll require 2
531    # just to avoid corner cases.
532    phys_mem_size = sum(map(lambda mem: mem.range.size(),
533                            self.memories.unproxy(self)))
534    assert(phys_mem_size >= 0x200000)
535
536    self.e820_table.entries = \
537       [
538        # Mark the first megabyte of memory as reserved
539        X86E820Entry(addr = 0, size = '1MB', range_type = 2),
540        # Mark the rest as available
541        X86E820Entry(addr = 0x100000,
542                size = '%dB' % (phys_mem_size - 0x100000),
543                range_type = 1)
544        ]
545
546    # Command line
547    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
548                        'root=/dev/hda1'
549    return self
550
551
552def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
553    self = Root(full_system = full_system)
554    self.testsys = testSystem
555    self.drivesys = driveSystem
556    self.etherlink = EtherLink()
557    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
558    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
559
560    if hasattr(testSystem, 'realview'):
561        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
562        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
563    elif hasattr(testSystem, 'tsunami'):
564        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
565        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
566    else:
567        fatal("Don't know how to connect these system together")
568
569    if dumpfile:
570        self.etherdump = EtherDump(file=dumpfile)
571        self.etherlink.dump = Parent.etherdump
572
573    return self
574