FSConfig.py revision 4444
13898Ssaidi@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 22934Sktlim@umich.edu# All rights reserved. 32934Sktlim@umich.edu# 42934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 52934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 62934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 72934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 82934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 92934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 102934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 112934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 122934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 132934Sktlim@umich.edu# this software without specific prior written permission. 142934Sktlim@umich.edu# 152934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262934Sktlim@umich.edu# 272934Sktlim@umich.edu# Authors: Kevin Lim 282934Sktlim@umich.edu 292934Sktlim@umich.eduimport m5 302969Sktlim@umich.edufrom m5 import makeList 312934Sktlim@umich.edufrom m5.objects import * 322995Ssaidi@eecs.umich.edufrom Benchmarks import * 332934Sktlim@umich.edu 342934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 352934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 362934Sktlim@umich.edu read_only=False) 372934Sktlim@umich.edu 382934Sktlim@umich.edu def childImage(self, ci): 392934Sktlim@umich.edu self.image.child.image_file = ci 402934Sktlim@umich.edu 413898Ssaidi@eecs.umich.educlass CowMmDisk(MmDisk): 423898Ssaidi@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 433898Ssaidi@eecs.umich.edu read_only=False) 443898Ssaidi@eecs.umich.edu 453898Ssaidi@eecs.umich.edu def childImage(self, ci): 463898Ssaidi@eecs.umich.edu self.image.child.image_file = ci 473898Ssaidi@eecs.umich.edu 483898Ssaidi@eecs.umich.edu 492934Sktlim@umich.educlass BaseTsunami(Tsunami): 502934Sktlim@umich.edu ethernet = NSGigE(configdata=NSGigEPciData(), 512934Sktlim@umich.edu pci_bus=0, pci_dev=1, pci_func=0) 522934Sktlim@umich.edu etherint = NSGigEInt(device=Parent.ethernet) 532934Sktlim@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 542934Sktlim@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 552934Sktlim@umich.edu 563005Sstever@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 572934Sktlim@umich.edu self = LinuxAlphaSystem() 583005Sstever@eecs.umich.edu if not mdesc: 593005Sstever@eecs.umich.edu # generic system 603304Sstever@eecs.umich.edu mdesc = SysConfig() 612995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 622934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 632934Sktlim@umich.edu self.membus = Bus(bus_id=1) 644444Ssaidi@eecs.umich.edu self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') 652995Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 662934Sktlim@umich.edu self.bridge.side_a = self.iobus.port 672934Sktlim@umich.edu self.bridge.side_b = self.membus.port 682934Sktlim@umich.edu self.physmem.port = self.membus.port 692934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 702934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 712995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 722934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 732934Sktlim@umich.edu self.tsunami = BaseTsunami() 742934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 752934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 762934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 772995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 782934Sktlim@umich.edu read_only = True)) 792934Sktlim@umich.edu self.intrctrl = IntrControl() 802953Sktlim@umich.edu self.mem_mode = mem_mode 814094Sbinkertn@umich.edu self.sim_console = SimConsole() 822934Sktlim@umich.edu self.kernel = binary('vmlinux') 833449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 842934Sktlim@umich.edu self.console = binary('console') 852934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 862934Sktlim@umich.edu 872934Sktlim@umich.edu return self 882934Sktlim@umich.edu 893584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 903584Ssaidi@eecs.umich.edu self = SparcSystem() 913584Ssaidi@eecs.umich.edu if not mdesc: 923584Ssaidi@eecs.umich.edu # generic system 933584Ssaidi@eecs.umich.edu mdesc = SysConfig() 943584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 953743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 963584Ssaidi@eecs.umich.edu self.membus = Bus(bus_id=1) 974444Ssaidi@eecs.umich.edu self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') 983743Sgblack@eecs.umich.edu self.t1000 = T1000() 994104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1003743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1013823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1023814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1033743Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1043743Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1053584Ssaidi@eecs.umich.edu self.physmem.port = self.membus.port 1063814Ssaidi@eecs.umich.edu self.physmem2.port = self.membus.port 1073584Ssaidi@eecs.umich.edu self.rom.port = self.membus.port 1083745Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1093745Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1103745Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1113584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1123898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1133898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1143898Ssaidi@eecs.umich.edu self.disk0.pio = self.iobus.port 1154103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1164103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1174103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1183745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1193745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1203745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1213584Ssaidi@eecs.umich.edu 1223584Ssaidi@eecs.umich.edu return self 1233584Ssaidi@eecs.umich.edu 1243584Ssaidi@eecs.umich.edu 1253025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 1262934Sktlim@umich.edu self = Root() 1272995Ssaidi@eecs.umich.edu self.testsys = testSystem 1282995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 1293025Ssaidi@eecs.umich.edu self.etherlink = EtherLink(int1 = Parent.testsys.tsunami.etherint[0], 1303025Ssaidi@eecs.umich.edu int2 = Parent.drivesys.tsunami.etherint[0]) 1313025Ssaidi@eecs.umich.edu if dumpfile: 1323025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 1333025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 1342934Sktlim@umich.edu 1352934Sktlim@umich.edu return self 136