CpuConfig.py revision 12564:2778478ca882
1# Copyright (c) 2012, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38from __future__ import print_function
39
40from m5 import fatal
41import m5.objects
42import inspect
43import sys
44from textwrap import TextWrapper
45
46# Dictionary of mapping names of real CPU models to classes.
47_cpu_classes = {}
48
49
50def is_cpu_class(cls):
51    """Determine if a class is a CPU that can be instantiated"""
52
53    # We can't use the normal inspect.isclass because the ParamFactory
54    # and ProxyFactory classes have a tendency to confuse it.
55    try:
56        return issubclass(cls, m5.objects.BaseCPU) and \
57            not cls.abstract and \
58            not issubclass(cls, m5.objects.CheckerCPU)
59    except (TypeError, AttributeError):
60        return False
61
62def get(name):
63    """Get a CPU class from a user provided class name or alias."""
64
65    try:
66        cpu_class = _cpu_classes[name]
67        return cpu_class
68    except KeyError:
69        print("%s is not a valid CPU model." % (name,))
70        sys.exit(1)
71
72def print_cpu_list():
73    """Print a list of available CPU classes including their aliases."""
74
75    print("Available CPU classes:")
76    doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
77    for name, cls in _cpu_classes.items():
78        print("\t%s" % name)
79
80        # Try to extract the class documentation from the class help
81        # string.
82        doc = inspect.getdoc(cls)
83        if doc:
84            for line in doc_wrapper.wrap(doc):
85                print(line)
86
87def cpu_names():
88    """Return a list of valid CPU names."""
89    return _cpu_classes.keys()
90
91def config_etrace(cpu_cls, cpu_list, options):
92    if issubclass(cpu_cls, m5.objects.DerivO3CPU):
93        # Assign the same file name to all cpus for now. This must be
94        # revisited when creating elastic traces for multi processor systems.
95        for cpu in cpu_list:
96            # Attach the elastic trace probe listener. Set the protobuf trace
97            # file names. Set the dependency window size equal to the cpu it
98            # is attached to.
99            cpu.traceListener = m5.objects.ElasticTrace(
100                                instFetchTraceFile = options.inst_trace_file,
101                                dataDepTraceFile = options.data_trace_file,
102                                depWindowSize = 3 * cpu.numROBEntries)
103            # Make the number of entries in the ROB, LQ and SQ very
104            # large so that there are no stalls due to resource
105            # limitation as such stalls will get captured in the trace
106            # as compute delay. For replay, ROB, LQ and SQ sizes are
107            # modelled in the Trace CPU.
108            cpu.numROBEntries = 512;
109            cpu.LQEntries = 128;
110            cpu.SQEntries = 128;
111    else:
112        fatal("%s does not support data dependency tracing. Use a CPU model of"
113              " type or inherited from DerivO3CPU.", cpu_cls)
114
115# Add all CPUs in the object hierarchy.
116for name, cls in inspect.getmembers(m5.objects, is_cpu_class):
117    _cpu_classes[name] = cls
118
119
120from m5.defines import buildEnv
121from importlib import import_module
122for package in [ "generic", buildEnv['TARGET_ISA']]:
123    try:
124        package = import_module(".cores." + package, package=__package__)
125    except ImportError:
126        # No timing models for this ISA
127        continue
128
129    for mod_name, module in inspect.getmembers(package, inspect.ismodule):
130        for name, cls in inspect.getmembers(module, is_cpu_class):
131            _cpu_classes[name] = cls
132