CpuConfig.py revision 9520
12068SN/A# Copyright (c) 2012 ARM Limited 22068SN/A# All rights reserved. 32188SN/A# 42068SN/A# The license below extends only to copyright in the software and shall 52068SN/A# not be construed as granting a license to any other intellectual 62068SN/A# property including but not limited to intellectual property relating 72068SN/A# to a hardware implementation of the functionality of the software 82068SN/A# licensed hereunder. You may use the software subject to the license 92068SN/A# terms below provided that you ensure that this notice is replicated 102068SN/A# unmodified and in its entirety in all distributions of the software, 112068SN/A# modified or unmodified, in source code or in binary form. 122068SN/A# 132068SN/A# Redistribution and use in source and binary forms, with or without 142068SN/A# modification, are permitted provided that the following conditions are 152068SN/A# met: redistributions of source code must retain the above copyright 162068SN/A# notice, this list of conditions and the following disclaimer; 172068SN/A# redistributions in binary form must reproduce the above copyright 182068SN/A# notice, this list of conditions and the following disclaimer in the 192068SN/A# documentation and/or other materials provided with the distribution; 202068SN/A# neither the name of the copyright holders nor the names of its 212068SN/A# contributors may be used to endorse or promote products derived from 222068SN/A# this software without specific prior written permission. 232068SN/A# 242068SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252068SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262068SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272068SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282665Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292665Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302068SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 312649Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 322649Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 332649Ssaidi@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 342649Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 352649Ssaidi@eecs.umich.edu# 362068SN/A# Authors: Andreas Sandberg 372068SN/A 382068SN/Aimport m5.objects 392068SN/Aimport inspect 402068SN/Aimport sys 412068SN/Afrom textwrap import TextWrapper 422068SN/A 432068SN/A# Dictionary of mapping names of real CPU models to classes. 448588Sgblack@eecs.umich.edu_cpu_classes = {} 458588Sgblack@eecs.umich.edu 468588Sgblack@eecs.umich.edu# CPU aliases. The CPUs listed here might not be compiled, we make 478588Sgblack@eecs.umich.edu# sure they exist before we add them to the CPU list. A target may be 488588Sgblack@eecs.umich.edu# specified as a tuple, in which case the first available CPU model in 498588Sgblack@eecs.umich.edu# the tuple will be used as the target. 502068SN/A_cpu_aliases_all = [ 512068SN/A ("timing", "TimingSimpleCPU"), 522068SN/A ("atomic", "AtomicSimpleCPU"), 538588Sgblack@eecs.umich.edu ("inorder", "InOrderCPU"), 548588Sgblack@eecs.umich.edu ("detailed", "DerivO3CPU"), 552068SN/A ] 562068SN/A 578588Sgblack@eecs.umich.edu# Filtered list of aliases. Only aliases for existing CPUs exist in 582075SN/A# this list. 592068SN/A_cpu_aliases = {} 602068SN/A 612068SN/A 628588Sgblack@eecs.umich.edudef is_cpu_class(cls): 638588Sgblack@eecs.umich.edu """Determine if a class is a CPU that can be instantiated""" 648588Sgblack@eecs.umich.edu 658588Sgblack@eecs.umich.edu # We can't use the normal inspect.isclass because the ParamFactory 668588Sgblack@eecs.umich.edu # and ProxyFactory classes have a tendency to confuse it. 678588Sgblack@eecs.umich.edu try: 688588Sgblack@eecs.umich.edu return issubclass(cls, m5.objects.BaseCPU) and \ 692068SN/A not cls.abstract and \ 702068SN/A not issubclass(cls, m5.objects.CheckerCPU) 712068SN/A except TypeError: 728588Sgblack@eecs.umich.edu return False 732068SN/A 742069SN/Adef get(name): 752068SN/A """Get a CPU class from a user provided class name or alias.""" 762068SN/A 774027Sstever@eecs.umich.edu real_name = _cpu_aliases.get(name, name) 784027Sstever@eecs.umich.edu 794027Sstever@eecs.umich.edu try: 806076Sgblack@eecs.umich.edu cpu_class = _cpu_classes[real_name] 818588Sgblack@eecs.umich.edu return cpu_class 822068SN/A except KeyError: 832069SN/A print "%s is not a valid CPU model." % (name,) 842068SN/A sys.exit(1) 852068SN/A 862068SN/Adef print_cpu_list(): 872068SN/A """Print a list of available CPU classes including their aliases.""" 882068SN/A 892068SN/A print "Available CPU classes:" 902068SN/A doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t") 912068SN/A for name, cls in _cpu_classes.items(): 924027Sstever@eecs.umich.edu print "\t%s" % name 934027Sstever@eecs.umich.edu 944027Sstever@eecs.umich.edu # Try to extract the class documentation from the class help 954027Sstever@eecs.umich.edu # string. 964027Sstever@eecs.umich.edu doc = inspect.getdoc(cls) 974027Sstever@eecs.umich.edu if doc: 986076Sgblack@eecs.umich.edu for line in doc_wrapper.wrap(doc): 992068SN/A print line 1002068SN/A 1012068SN/A if _cpu_aliases: 1022068SN/A print "\nCPU aliases:" 1037799Sgblack@eecs.umich.edu for alias, target in _cpu_aliases.items(): 1042068SN/A print "\t%s => %s" % (alias, target) 1058588Sgblack@eecs.umich.edu 1062068SN/Adef cpu_names(): 1078588Sgblack@eecs.umich.edu """Return a list of valid CPU names.""" 1082068SN/A return _cpu_classes.keys() + _cpu_aliases.keys() 1092068SN/A 1108588Sgblack@eecs.umich.edu# The ARM detailed CPU is special in the sense that it doesn't exist 1112147SN/A# in the normal object hierarchy, so we have to add it manually. 1128588Sgblack@eecs.umich.edutry: 1132068SN/A from O3_ARM_v7a import O3_ARM_v7a_3 1148588Sgblack@eecs.umich.edu _cpu_classes["arm_detailed"] = O3_ARM_v7a_3 1158588Sgblack@eecs.umich.eduexcept: 1162068SN/A pass 1172068SN/A 1182068SN/A# Add all CPUs in the object hierarchy. 1192068SN/Afor name, cls in inspect.getmembers(m5.objects, is_cpu_class): 1202068SN/A _cpu_classes[name] = cls 1212068SN/A 1222068SN/Afor alias, target in _cpu_aliases_all: 1232147SN/A if isinstance(target, tuple): 1242068SN/A # Some aliases contain a list of CPU model sorted in priority 1252068SN/A # order. Use the first target that's available. 1262068SN/A for t in target: 1272068SN/A if t in _cpu_classes: 1282068SN/A _cpu_aliases[alias] = t 1298588Sgblack@eecs.umich.edu break 1302068SN/A elif target in _cpu_classes: 1318588Sgblack@eecs.umich.edu # Normal alias 1322068SN/A _cpu_aliases[alias] = target 1332068SN/A