CpuConfig.py revision 12095
19520SAndreas.Sandberg@ARM.com# Copyright (c) 2012 ARM Limited 29520SAndreas.Sandberg@ARM.com# All rights reserved. 39520SAndreas.Sandberg@ARM.com# 49520SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59520SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69520SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79520SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89520SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99520SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109520SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119520SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129520SAndreas.Sandberg@ARM.com# 139520SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 149520SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 159520SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 169520SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 179520SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 189520SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 199520SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 209520SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 219520SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 229520SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 239520SAndreas.Sandberg@ARM.com# 249520SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259520SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269520SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279520SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289520SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299520SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309520SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319520SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329520SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339520SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349520SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359520SAndreas.Sandberg@ARM.com# 369520SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg 379520SAndreas.Sandberg@ARM.com 3812095Sandreas.sandberg@arm.comfrom m5 import fatal 399520SAndreas.Sandberg@ARM.comimport m5.objects 409520SAndreas.Sandberg@ARM.comimport inspect 419520SAndreas.Sandberg@ARM.comimport sys 4211995Sgabeblack@google.comfrom textwrap import TextWrapper 439520SAndreas.Sandberg@ARM.com 449520SAndreas.Sandberg@ARM.com# Dictionary of mapping names of real CPU models to classes. 459520SAndreas.Sandberg@ARM.com_cpu_classes = {} 469520SAndreas.Sandberg@ARM.com 479520SAndreas.Sandberg@ARM.com 489520SAndreas.Sandberg@ARM.comdef is_cpu_class(cls): 499520SAndreas.Sandberg@ARM.com """Determine if a class is a CPU that can be instantiated""" 509520SAndreas.Sandberg@ARM.com 519520SAndreas.Sandberg@ARM.com # We can't use the normal inspect.isclass because the ParamFactory 529520SAndreas.Sandberg@ARM.com # and ProxyFactory classes have a tendency to confuse it. 539520SAndreas.Sandberg@ARM.com try: 549520SAndreas.Sandberg@ARM.com return issubclass(cls, m5.objects.BaseCPU) and \ 559520SAndreas.Sandberg@ARM.com not cls.abstract and \ 569520SAndreas.Sandberg@ARM.com not issubclass(cls, m5.objects.CheckerCPU) 5711688Sandreas.hansson@arm.com except (TypeError, AttributeError): 589520SAndreas.Sandberg@ARM.com return False 599520SAndreas.Sandberg@ARM.com 609520SAndreas.Sandberg@ARM.comdef get(name): 619520SAndreas.Sandberg@ARM.com """Get a CPU class from a user provided class name or alias.""" 629520SAndreas.Sandberg@ARM.com 639520SAndreas.Sandberg@ARM.com try: 6411995Sgabeblack@google.com cpu_class = _cpu_classes[name] 659520SAndreas.Sandberg@ARM.com return cpu_class 669520SAndreas.Sandberg@ARM.com except KeyError: 679520SAndreas.Sandberg@ARM.com print "%s is not a valid CPU model." % (name,) 689520SAndreas.Sandberg@ARM.com sys.exit(1) 699520SAndreas.Sandberg@ARM.com 709520SAndreas.Sandberg@ARM.comdef print_cpu_list(): 719520SAndreas.Sandberg@ARM.com """Print a list of available CPU classes including their aliases.""" 729520SAndreas.Sandberg@ARM.com 739520SAndreas.Sandberg@ARM.com print "Available CPU classes:" 749520SAndreas.Sandberg@ARM.com doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t") 759520SAndreas.Sandberg@ARM.com for name, cls in _cpu_classes.items(): 769520SAndreas.Sandberg@ARM.com print "\t%s" % name 779520SAndreas.Sandberg@ARM.com 789520SAndreas.Sandberg@ARM.com # Try to extract the class documentation from the class help 799520SAndreas.Sandberg@ARM.com # string. 809520SAndreas.Sandberg@ARM.com doc = inspect.getdoc(cls) 819520SAndreas.Sandberg@ARM.com if doc: 829520SAndreas.Sandberg@ARM.com for line in doc_wrapper.wrap(doc): 839520SAndreas.Sandberg@ARM.com print line 849520SAndreas.Sandberg@ARM.com 859520SAndreas.Sandberg@ARM.comdef cpu_names(): 869520SAndreas.Sandberg@ARM.com """Return a list of valid CPU names.""" 8711995Sgabeblack@google.com return _cpu_classes.keys() 889520SAndreas.Sandberg@ARM.com 8911251Sradhika.jagtap@ARM.comdef config_etrace(cpu_cls, cpu_list, options): 9011251Sradhika.jagtap@ARM.com if issubclass(cpu_cls, m5.objects.DerivO3CPU): 9111251Sradhika.jagtap@ARM.com # Assign the same file name to all cpus for now. This must be 9211251Sradhika.jagtap@ARM.com # revisited when creating elastic traces for multi processor systems. 9311251Sradhika.jagtap@ARM.com for cpu in cpu_list: 9411251Sradhika.jagtap@ARM.com # Attach the elastic trace probe listener. Set the protobuf trace 9511251Sradhika.jagtap@ARM.com # file names. Set the dependency window size equal to the cpu it 9611251Sradhika.jagtap@ARM.com # is attached to. 9711251Sradhika.jagtap@ARM.com cpu.traceListener = m5.objects.ElasticTrace( 9811251Sradhika.jagtap@ARM.com instFetchTraceFile = options.inst_trace_file, 9911251Sradhika.jagtap@ARM.com dataDepTraceFile = options.data_trace_file, 10011251Sradhika.jagtap@ARM.com depWindowSize = 3 * cpu.numROBEntries) 10111251Sradhika.jagtap@ARM.com # Make the number of entries in the ROB, LQ and SQ very 10211251Sradhika.jagtap@ARM.com # large so that there are no stalls due to resource 10311251Sradhika.jagtap@ARM.com # limitation as such stalls will get captured in the trace 10411251Sradhika.jagtap@ARM.com # as compute delay. For replay, ROB, LQ and SQ sizes are 10511251Sradhika.jagtap@ARM.com # modelled in the Trace CPU. 10611251Sradhika.jagtap@ARM.com cpu.numROBEntries = 512; 10711251Sradhika.jagtap@ARM.com cpu.LQEntries = 128; 10811251Sradhika.jagtap@ARM.com cpu.SQEntries = 128; 10911251Sradhika.jagtap@ARM.com else: 11011251Sradhika.jagtap@ARM.com fatal("%s does not support data dependency tracing. Use a CPU model of" 11111251Sradhika.jagtap@ARM.com " type or inherited from DerivO3CPU.", cpu_cls) 11211251Sradhika.jagtap@ARM.com 1139520SAndreas.Sandberg@ARM.com# The ARM detailed CPU is special in the sense that it doesn't exist 1149520SAndreas.Sandberg@ARM.com# in the normal object hierarchy, so we have to add it manually. 1159520SAndreas.Sandberg@ARM.comtry: 1169520SAndreas.Sandberg@ARM.com from O3_ARM_v7a import O3_ARM_v7a_3 11711995Sgabeblack@google.com _cpu_classes["O3_ARM_v7a_3"] = O3_ARM_v7a_3 1189520SAndreas.Sandberg@ARM.comexcept: 1199520SAndreas.Sandberg@ARM.com pass 1209520SAndreas.Sandberg@ARM.com 12112028Spierre-yves.peneau@lirmm.fr# The calibrated ex5-model cores 12212028Spierre-yves.peneau@lirmm.frtry: 12312028Spierre-yves.peneau@lirmm.fr from ex5_LITTLE import ex5_LITTLE 12412028Spierre-yves.peneau@lirmm.fr _cpu_classes["ex5_LITTLE"] = ex5_LITTLE 12512028Spierre-yves.peneau@lirmm.frexcept: 12612028Spierre-yves.peneau@lirmm.fr pass 12712028Spierre-yves.peneau@lirmm.fr 12812028Spierre-yves.peneau@lirmm.frtry: 12912028Spierre-yves.peneau@lirmm.fr from ex5_big import ex5_big 13012028Spierre-yves.peneau@lirmm.fr _cpu_classes["ex5_big"] = ex5_big 13112028Spierre-yves.peneau@lirmm.frexcept: 13212028Spierre-yves.peneau@lirmm.fr pass 13312028Spierre-yves.peneau@lirmm.fr 13412028Spierre-yves.peneau@lirmm.fr 1359520SAndreas.Sandberg@ARM.com# Add all CPUs in the object hierarchy. 1369520SAndreas.Sandberg@ARM.comfor name, cls in inspect.getmembers(m5.objects, is_cpu_class): 1379520SAndreas.Sandberg@ARM.com _cpu_classes[name] = cls 138