Caches.py revision 11722:f15f02d8c79e 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
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23# neither the name of the copyright holders nor the names of its
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25# this software without specific prior written permission.
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27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38#
39# Authors: Lisa Hsu
40
41from m5.objects import *
42
43# Base implementations of L1, L2, IO and TLB-walker caches. There are
44# used in the regressions and also as base components in the
45# system-configuration scripts. The values are meant to serve as a
46# starting point, and specific parameters can be overridden in the
47# specific instantiations.
48
49class L1Cache(Cache):
50    assoc = 2
51    tag_latency = 2
52    data_latency = 2
53    response_latency = 2
54    mshrs = 4
55    tgts_per_mshr = 20
56
57class L1_ICache(L1Cache):
58    is_read_only = True
59    # Writeback clean lines as well
60    writeback_clean = True
61
62class L1_DCache(L1Cache):
63    pass
64
65class L2Cache(Cache):
66    assoc = 8
67    tag_latency = 20
68    data_latency = 20
69    response_latency = 20
70    mshrs = 20
71    tgts_per_mshr = 12
72    write_buffers = 8
73
74class IOCache(Cache):
75    assoc = 8
76    tag_latency = 50
77    data_latency = 50
78    response_latency = 50
79    mshrs = 20
80    size = '1kB'
81    tgts_per_mshr = 12
82
83class PageTableWalkerCache(Cache):
84    assoc = 2
85    tag_latency = 2
86    data_latency = 2
87    response_latency = 2
88    mshrs = 10
89    size = '1kB'
90    tgts_per_mshr = 12
91
92    # the x86 table walker actually writes to the table-walker cache
93    if buildEnv['TARGET_ISA'] == 'x86':
94        is_read_only = False
95    else:
96        is_read_only = True
97        # Writeback clean lines as well
98        writeback_clean = True
99