Caches.py revision 11331:cd5c48db28e6 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
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8# licensed hereunder.  You may use the software subject to the license
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11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
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38#
39# Authors: Lisa Hsu
40
41from m5.objects import *
42
43# Base implementations of L1, L2, IO and TLB-walker caches. There are
44# used in the regressions and also as base components in the
45# system-configuration scripts. The values are meant to serve as a
46# starting point, and specific parameters can be overridden in the
47# specific instantiations.
48
49class L1Cache(Cache):
50    assoc = 2
51    hit_latency = 2
52    response_latency = 2
53    mshrs = 4
54    tgts_per_mshr = 20
55
56class L1_ICache(L1Cache):
57    is_read_only = True
58    # Writeback clean lines as well
59    writeback_clean = True
60
61class L1_DCache(L1Cache):
62    pass
63
64class L2Cache(Cache):
65    assoc = 8
66    hit_latency = 20
67    response_latency = 20
68    mshrs = 20
69    tgts_per_mshr = 12
70    write_buffers = 8
71
72class IOCache(Cache):
73    assoc = 8
74    hit_latency = 50
75    response_latency = 50
76    mshrs = 20
77    size = '1kB'
78    tgts_per_mshr = 12
79
80class PageTableWalkerCache(Cache):
81    assoc = 2
82    hit_latency = 2
83    response_latency = 2
84    mshrs = 10
85    size = '1kB'
86    tgts_per_mshr = 12
87
88    # the x86 table walker actually writes to the table-walker cache
89    if buildEnv['TARGET_ISA'] == 'x86':
90        is_read_only = False
91    else:
92        is_read_only = True
93        # Writeback clean lines as well
94        writeback_clean = True
95