CacheConfig.py revision 8863:50ce4deacda9 
1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29# Configure the M5 cache hierarchy config in one place
30#
31
32import m5
33from m5.objects import *
34from Caches import *
35from O3_ARM_v7a import *
36
37def config_cache(options, system):
38    if options.l2cache:
39        if options.cpu_type == "arm_detailed":
40            system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc,
41                                block_size=options.cacheline_size)
42        else:
43            system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
44                                block_size=options.cacheline_size)
45
46        system.tol2bus = Bus()
47        system.l2.cpu_side = system.tol2bus.master
48        system.l2.mem_side = system.membus.slave
49
50    for i in xrange(options.num_cpus):
51        if options.caches:
52            if options.cpu_type == "arm_detailed":
53                icache = O3_ARM_v7a_ICache(size = options.l1i_size,
54                                     assoc = options.l1i_assoc,
55                                     block_size=options.cacheline_size)
56                dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
57                                     assoc = options.l1d_assoc,
58                                     block_size=options.cacheline_size)
59            else:
60                icache = L1Cache(size = options.l1i_size,
61                                 assoc = options.l1i_assoc,
62                                 block_size=options.cacheline_size)
63                dcache = L1Cache(size = options.l1d_size,
64                                 assoc = options.l1d_assoc,
65                                 block_size=options.cacheline_size)
66
67            if buildEnv['TARGET_ISA'] == 'x86':
68                system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
69                                                      PageTableWalkerCache(),
70                                                      PageTableWalkerCache())
71            else:
72                system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
73        system.cpu[i].createInterruptController()
74        if options.l2cache:
75            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
76        else:
77            system.cpu[i].connectAllPorts(system.membus)
78
79    return system
80