CacheConfig.py revision 8057:5a8208fa1600 
1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
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14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Lisa Hsu
28
29# Configure the M5 cache hierarchy config in one place
30#
31
32import m5
33from m5.objects import *
34from Caches import *
35
36def config_cache(options, system):
37    if options.l2cache:
38        system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
39                            block_size=options.cacheline_size)
40        system.tol2bus = Bus()
41        system.l2.cpu_side = system.tol2bus.port
42        system.l2.mem_side = system.membus.port
43        system.l2.num_cpus = options.num_cpus
44
45    for i in xrange(options.num_cpus):
46        if options.caches:
47            icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc,
48                             block_size=options.cacheline_size)
49            dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
50                             block_size=options.cacheline_size)
51            if buildEnv['TARGET_ISA'] == 'x86':
52                system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
53                                                      PageTableWalkerCache(),
54                                                      PageTableWalkerCache())
55            else:
56                system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
57        if options.l2cache:
58            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
59        else:
60            system.cpu[i].connectAllPorts(system.membus)
61
62    return system
63