CacheConfig.py revision 6981:aba5f7216636 
1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Lisa Hsu
28
29# Configure the M5 cache hierarchy config in one place
30#
31
32import m5
33from m5.objects import *
34from Caches import *
35
36def config_cache(options, system):
37    if options.l2cache:
38        system.l2 = L2Cache(size='2MB')
39        system.tol2bus = Bus()
40        system.l2.cpu_side = system.tol2bus.port
41        system.l2.mem_side = system.membus.port
42        system.l2.num_cpus = options.num_cpus
43
44    for i in xrange(options.num_cpus):
45        if options.caches:
46            system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
47                                                  L1Cache(size = '64kB'))
48        if options.l2cache:
49            system.cpu[i].connectMemPorts(system.tol2bus)
50        else:
51            system.cpu[i].connectMemPorts(system.membus)
52
53    return system
54