CacheConfig.py revision 13806:e2ca4f169e82 
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13# Copyright (c) 2010 Advanced Micro Devices, Inc.
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38#
39# Authors: Lisa Hsu
40
41# Configure the M5 cache hierarchy config in one place
42#
43
44from __future__ import print_function
45from __future__ import absolute_import
46
47import m5
48from m5.objects import *
49from .Caches import *
50
51def config_cache(options, system):
52    if options.external_memory_system and (options.caches or options.l2cache):
53        print("External caches and internal caches are exclusive options.\n")
54        sys.exit(1)
55
56    if options.external_memory_system:
57        ExternalCache = ExternalCacheFactory(options.external_memory_system)
58
59    if options.cpu_type == "O3_ARM_v7a_3":
60        try:
61            import cores.arm.O3_ARM_v7a as core
62        except:
63            print("O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?")
64            sys.exit(1)
65
66        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
67            core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
68            core.O3_ARM_v7aL2, \
69            core.O3_ARM_v7aWalkCache
70    else:
71        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
72            L1_DCache, L1_ICache, L2Cache, None
73
74        if buildEnv['TARGET_ISA'] == 'x86':
75            walk_cache_class = PageTableWalkerCache
76
77    # Set the cache line size of the system
78    system.cache_line_size = options.cacheline_size
79
80    # If elastic trace generation is enabled, make sure the memory system is
81    # minimal so that compute delays do not include memory access latencies.
82    # Configure the compulsory L1 caches for the O3CPU, do not configure
83    # any more caches.
84    if options.l2cache and options.elastic_trace_en:
85        fatal("When elastic trace is enabled, do not configure L2 caches.")
86
87    if options.l2cache:
88        # Provide a clock for the L2 and the L1-to-L2 bus here as they
89        # are not connected using addTwoLevelCacheHierarchy. Use the
90        # same clock as the CPUs.
91        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
92                                   size=options.l2_size,
93                                   assoc=options.l2_assoc)
94
95        system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
96        system.l2.cpu_side = system.tol2bus.master
97        system.l2.mem_side = system.membus.slave
98
99    if options.memchecker:
100        system.memchecker = MemChecker()
101
102    for i in range(options.num_cpus):
103        if options.caches:
104            icache = icache_class(size=options.l1i_size,
105                                  assoc=options.l1i_assoc)
106            dcache = dcache_class(size=options.l1d_size,
107                                  assoc=options.l1d_assoc)
108
109            # If we have a walker cache specified, instantiate two
110            # instances here
111            if walk_cache_class:
112                iwalkcache = walk_cache_class()
113                dwalkcache = walk_cache_class()
114            else:
115                iwalkcache = None
116                dwalkcache = None
117
118            if options.memchecker:
119                dcache_mon = MemCheckerMonitor(warn_only=True)
120                dcache_real = dcache
121
122                # Do not pass the memchecker into the constructor of
123                # MemCheckerMonitor, as it would create a copy; we require
124                # exactly one MemChecker instance.
125                dcache_mon.memchecker = system.memchecker
126
127                # Connect monitor
128                dcache_mon.mem_side = dcache.cpu_side
129
130                # Let CPU connect to monitors
131                dcache = dcache_mon
132
133            # When connecting the caches, the clock is also inherited
134            # from the CPU in question
135            system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
136                                                  iwalkcache, dwalkcache)
137
138            if options.memchecker:
139                # The mem_side ports of the caches haven't been connected yet.
140                # Make sure connectAllPorts connects the right objects.
141                system.cpu[i].dcache = dcache_real
142                system.cpu[i].dcache_mon = dcache_mon
143
144        elif options.external_memory_system:
145            # These port names are presented to whatever 'external' system
146            # gem5 is connecting to.  Its configuration will likely depend
147            # on these names.  For simplicity, we would advise configuring
148            # it to use this naming scheme; if this isn't possible, change
149            # the names below.
150            if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
151                system.cpu[i].addPrivateSplitL1Caches(
152                        ExternalCache("cpu%d.icache" % i),
153                        ExternalCache("cpu%d.dcache" % i),
154                        ExternalCache("cpu%d.itb_walker_cache" % i),
155                        ExternalCache("cpu%d.dtb_walker_cache" % i))
156            else:
157                system.cpu[i].addPrivateSplitL1Caches(
158                        ExternalCache("cpu%d.icache" % i),
159                        ExternalCache("cpu%d.dcache" % i))
160
161        system.cpu[i].createInterruptController()
162        if options.l2cache:
163            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
164        elif options.external_memory_system:
165            system.cpu[i].connectUncachedPorts(system.membus)
166        else:
167            system.cpu[i].connectAllPorts(system.membus)
168
169    return system
170
171# ExternalSlave provides a "port", but when that port connects to a cache,
172# the connecting CPU SimObject wants to refer to its "cpu_side".
173# The 'ExternalCache' class provides this adaptation by rewriting the name,
174# eliminating distracting changes elsewhere in the config code.
175class ExternalCache(ExternalSlave):
176    def __getattr__(cls, attr):
177        if (attr == "cpu_side"):
178            attr = "port"
179        return super(ExternalSlave, cls).__getattr__(attr)
180
181    def __setattr__(cls, attr, value):
182        if (attr == "cpu_side"):
183            attr = "port"
184        return super(ExternalSlave, cls).__setattr__(attr, value)
185
186def ExternalCacheFactory(port_type):
187    def make(name):
188        return ExternalCache(port_data=name, port_type=port_type,
189                             addr_ranges=[AllMemory])
190    return make
191