CacheConfig.py revision 12014:f973caaf935d 
1# Copyright (c) 2012-2013, 2015-2016 ARM Limited
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13# Copyright (c) 2010 Advanced Micro Devices, Inc.
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38#
39# Authors: Lisa Hsu
40
41# Configure the M5 cache hierarchy config in one place
42#
43
44import m5
45from m5.objects import *
46from Caches import *
47
48def config_cache(options, system):
49    if options.external_memory_system and (options.caches or options.l2cache):
50        print "External caches and internal caches are exclusive options.\n"
51        sys.exit(1)
52
53    if options.external_memory_system:
54        ExternalCache = ExternalCacheFactory(options.external_memory_system)
55
56    if options.cpu_type == "O3_ARM_v7a_3":
57        try:
58            from O3_ARM_v7a import *
59        except:
60            print "arm_detailed is unavailable. Did you compile the O3 model?"
61            sys.exit(1)
62
63        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
64            O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
65            O3_ARM_v7aWalkCache
66    else:
67        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
68            L1_DCache, L1_ICache, L2Cache, None
69
70        if buildEnv['TARGET_ISA'] == 'x86':
71            walk_cache_class = PageTableWalkerCache
72
73    # Set the cache line size of the system
74    system.cache_line_size = options.cacheline_size
75
76    # If elastic trace generation is enabled, make sure the memory system is
77    # minimal so that compute delays do not include memory access latencies.
78    # Configure the compulsory L1 caches for the O3CPU, do not configure
79    # any more caches.
80    if options.l2cache and options.elastic_trace_en:
81        fatal("When elastic trace is enabled, do not configure L2 caches.")
82
83    if options.l2cache:
84        # Provide a clock for the L2 and the L1-to-L2 bus here as they
85        # are not connected using addTwoLevelCacheHierarchy. Use the
86        # same clock as the CPUs.
87        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
88                                   size=options.l2_size,
89                                   assoc=options.l2_assoc)
90
91        system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
92        system.l2.cpu_side = system.tol2bus.master
93        system.l2.mem_side = system.membus.slave
94
95    if options.memchecker:
96        system.memchecker = MemChecker()
97
98    for i in xrange(options.num_cpus):
99        if options.caches:
100            icache = icache_class(size=options.l1i_size,
101                                  assoc=options.l1i_assoc)
102            dcache = dcache_class(size=options.l1d_size,
103                                  assoc=options.l1d_assoc)
104
105            # If we have a walker cache specified, instantiate two
106            # instances here
107            if walk_cache_class:
108                iwalkcache = walk_cache_class()
109                dwalkcache = walk_cache_class()
110            else:
111                iwalkcache = None
112                dwalkcache = None
113
114            if options.memchecker:
115                dcache_mon = MemCheckerMonitor(warn_only=True)
116                dcache_real = dcache
117
118                # Do not pass the memchecker into the constructor of
119                # MemCheckerMonitor, as it would create a copy; we require
120                # exactly one MemChecker instance.
121                dcache_mon.memchecker = system.memchecker
122
123                # Connect monitor
124                dcache_mon.mem_side = dcache.cpu_side
125
126                # Let CPU connect to monitors
127                dcache = dcache_mon
128
129            # When connecting the caches, the clock is also inherited
130            # from the CPU in question
131            system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
132                                                  iwalkcache, dwalkcache)
133
134            if options.memchecker:
135                # The mem_side ports of the caches haven't been connected yet.
136                # Make sure connectAllPorts connects the right objects.
137                system.cpu[i].dcache = dcache_real
138                system.cpu[i].dcache_mon = dcache_mon
139
140        elif options.external_memory_system:
141            # These port names are presented to whatever 'external' system
142            # gem5 is connecting to.  Its configuration will likely depend
143            # on these names.  For simplicity, we would advise configuring
144            # it to use this naming scheme; if this isn't possible, change
145            # the names below.
146            if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
147                system.cpu[i].addPrivateSplitL1Caches(
148                        ExternalCache("cpu%d.icache" % i),
149                        ExternalCache("cpu%d.dcache" % i),
150                        ExternalCache("cpu%d.itb_walker_cache" % i),
151                        ExternalCache("cpu%d.dtb_walker_cache" % i))
152            else:
153                system.cpu[i].addPrivateSplitL1Caches(
154                        ExternalCache("cpu%d.icache" % i),
155                        ExternalCache("cpu%d.dcache" % i))
156
157        system.cpu[i].createInterruptController()
158        if options.l2cache:
159            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
160        elif options.external_memory_system:
161            system.cpu[i].connectUncachedPorts(system.membus)
162        else:
163            system.cpu[i].connectAllPorts(system.membus)
164
165    return system
166
167# ExternalSlave provides a "port", but when that port connects to a cache,
168# the connecting CPU SimObject wants to refer to its "cpu_side".
169# The 'ExternalCache' class provides this adaptation by rewriting the name,
170# eliminating distracting changes elsewhere in the config code.
171class ExternalCache(ExternalSlave):
172    def __getattr__(cls, attr):
173        if (attr == "cpu_side"):
174            attr = "port"
175        return super(ExternalSlave, cls).__getattr__(attr)
176
177    def __setattr__(cls, attr, value):
178        if (attr == "cpu_side"):
179            attr = "port"
180        return super(ExternalSlave, cls).__setattr__(attr, value)
181
182def ExternalCacheFactory(port_type):
183    def make(name):
184        return ExternalCache(port_data=name, port_type=port_type,
185                             addr_ranges=[AllMemory])
186    return make
187