CacheConfig.py revision 10780:46070443051e 
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13# Copyright (c) 2010 Advanced Micro Devices, Inc.
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38#
39# Authors: Lisa Hsu
40
41# Configure the M5 cache hierarchy config in one place
42#
43
44import m5
45from m5.objects import *
46from Caches import *
47
48def config_cache(options, system):
49    if options.external_memory_system and (options.caches or options.l2cache):
50        print "External caches and internal caches are exclusive options.\n"
51        sys.exit(1)
52
53    if options.external_memory_system:
54        ExternalCache = ExternalCacheFactory(options.external_memory_system)
55
56    if options.cpu_type == "arm_detailed":
57        try:
58            from O3_ARM_v7a import *
59        except:
60            print "arm_detailed is unavailable. Did you compile the O3 model?"
61            sys.exit(1)
62
63        dcache_class, icache_class, l2_cache_class = \
64            O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
65    else:
66        dcache_class, icache_class, l2_cache_class = \
67            L1Cache, L1Cache, L2Cache
68
69    # Set the cache line size of the system
70    system.cache_line_size = options.cacheline_size
71
72    if options.l2cache:
73        # Provide a clock for the L2 and the L1-to-L2 bus here as they
74        # are not connected using addTwoLevelCacheHierarchy. Use the
75        # same clock as the CPUs.
76        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
77                                   size=options.l2_size,
78                                   assoc=options.l2_assoc)
79
80        system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
81        system.l2.cpu_side = system.tol2bus.master
82        system.l2.mem_side = system.membus.slave
83
84    if options.memchecker:
85        system.memchecker = MemChecker()
86
87    for i in xrange(options.num_cpus):
88        if options.caches:
89            icache = icache_class(size=options.l1i_size,
90                                  assoc=options.l1i_assoc)
91            dcache = dcache_class(size=options.l1d_size,
92                                  assoc=options.l1d_assoc)
93
94            if options.memchecker:
95                dcache_mon = MemCheckerMonitor(warn_only=True)
96                dcache_real = dcache
97
98                # Do not pass the memchecker into the constructor of
99                # MemCheckerMonitor, as it would create a copy; we require
100                # exactly one MemChecker instance.
101                dcache_mon.memchecker = system.memchecker
102
103                # Connect monitor
104                dcache_mon.mem_side = dcache.cpu_side
105
106                # Let CPU connect to monitors
107                dcache = dcache_mon
108
109            # When connecting the caches, the clock is also inherited
110            # from the CPU in question
111            if buildEnv['TARGET_ISA'] == 'x86':
112                system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
113                                                      PageTableWalkerCache(),
114                                                      PageTableWalkerCache())
115            else:
116                system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
117
118            if options.memchecker:
119                # The mem_side ports of the caches haven't been connected yet.
120                # Make sure connectAllPorts connects the right objects.
121                system.cpu[i].dcache = dcache_real
122                system.cpu[i].dcache_mon = dcache_mon
123
124        elif options.external_memory_system:
125            # These port names are presented to whatever 'external' system
126            # gem5 is connecting to.  Its configuration will likely depend
127            # on these names.  For simplicity, we would advise configuring
128            # it to use this naming scheme; if this isn't possible, change
129            # the names below.
130            if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
131                system.cpu[i].addPrivateSplitL1Caches(
132                        ExternalCache("cpu%d.icache" % i),
133                        ExternalCache("cpu%d.dcache" % i),
134                        ExternalCache("cpu%d.itb_walker_cache" % i),
135                        ExternalCache("cpu%d.dtb_walker_cache" % i))
136            else:
137                system.cpu[i].addPrivateSplitL1Caches(
138                        ExternalCache("cpu%d.icache" % i),
139                        ExternalCache("cpu%d.dcache" % i))
140
141        system.cpu[i].createInterruptController()
142        if options.l2cache:
143            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
144        elif options.external_memory_system:
145            system.cpu[i].connectUncachedPorts(system.membus)
146        else:
147            system.cpu[i].connectAllPorts(system.membus)
148
149    return system
150
151# ExternalSlave provides a "port", but when that port connects to a cache,
152# the connecting CPU SimObject wants to refer to its "cpu_side".
153# The 'ExternalCache' class provides this adaptation by rewriting the name,
154# eliminating distracting changes elsewhere in the config code.
155class ExternalCache(ExternalSlave):
156    def __getattr__(cls, attr):
157        if (attr == "cpu_side"):
158            attr = "port"
159        return super(ExternalSlave, cls).__getattr__(attr)
160
161    def __setattr__(cls, attr, value):
162        if (attr == "cpu_side"):
163            attr = "port"
164        return super(ExternalSlave, cls).__setattr__(attr, value)
165
166def ExternalCacheFactory(port_type):
167    def make(name):
168        return ExternalCache(port_data=name, port_type=port_type,
169                             addr_ranges=[AllMemory])
170    return make
171