CacheConfig.py revision 10613:9d0aef7a9b2e 
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13# Copyright (c) 2010 Advanced Micro Devices, Inc.
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39# Authors: Lisa Hsu
40
41# Configure the M5 cache hierarchy config in one place
42#
43
44import m5
45from m5.objects import *
46from Caches import *
47
48def config_cache(options, system):
49    if options.cpu_type == "arm_detailed":
50        try:
51            from O3_ARM_v7a import *
52        except:
53            print "arm_detailed is unavailable. Did you compile the O3 model?"
54            sys.exit(1)
55
56        dcache_class, icache_class, l2_cache_class = \
57            O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
58    else:
59        dcache_class, icache_class, l2_cache_class = \
60            L1Cache, L1Cache, L2Cache
61
62    # Set the cache line size of the system
63    system.cache_line_size = options.cacheline_size
64
65    if options.l2cache:
66        # Provide a clock for the L2 and the L1-to-L2 bus here as they
67        # are not connected using addTwoLevelCacheHierarchy. Use the
68        # same clock as the CPUs, and set the L1-to-L2 bus width to 32
69        # bytes (256 bits).
70        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
71                                   size=options.l2_size,
72                                   assoc=options.l2_assoc)
73
74        system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain,
75                                      width = 32)
76        system.l2.cpu_side = system.tol2bus.master
77        system.l2.mem_side = system.membus.slave
78
79    if options.memchecker:
80        system.memchecker = MemChecker()
81
82    for i in xrange(options.num_cpus):
83        if options.caches:
84            icache = icache_class(size=options.l1i_size,
85                                  assoc=options.l1i_assoc)
86            dcache = dcache_class(size=options.l1d_size,
87                                  assoc=options.l1d_assoc)
88
89            if options.memchecker:
90                dcache_mon = MemCheckerMonitor(warn_only=True)
91                dcache_real = dcache
92
93                # Do not pass the memchecker into the constructor of
94                # MemCheckerMonitor, as it would create a copy; we require
95                # exactly one MemChecker instance.
96                dcache_mon.memchecker = system.memchecker
97
98                # Connect monitor
99                dcache_mon.mem_side = dcache.cpu_side
100
101                # Let CPU connect to monitors
102                dcache = dcache_mon
103
104            # When connecting the caches, the clock is also inherited
105            # from the CPU in question
106            if buildEnv['TARGET_ISA'] == 'x86':
107                system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
108                                                      PageTableWalkerCache(),
109                                                      PageTableWalkerCache())
110            else:
111                system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
112
113            if options.memchecker:
114                # The mem_side ports of the caches haven't been connected yet.
115                # Make sure connectAllPorts connects the right objects.
116                system.cpu[i].dcache = dcache_real
117                system.cpu[i].dcache_mon = dcache_mon
118
119        system.cpu[i].createInterruptController()
120        if options.l2cache:
121            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
122        else:
123            system.cpu[i].connectAllPorts(system.membus)
124
125    return system
126