sim_control_if.hh revision 12047:8b269268312c 
1/*
2 * Copyright (c) 2017, Dresden University of Technology (TU Dresden)
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
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9 * 1. Redistributions of source code must retain the above copyright notice,
10 *    this list of conditions and the following disclaimer.
11 *
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * 3. Neither the name of the copyright holder nor the names of its
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18 *    this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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24 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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31 *
32 * Authors: Christian Menard
33 */
34
35#ifndef __SC_SIM_CONTROL_IF_HH__
36#define __SC_SIM_CONTROL_IF_HH__
37
38#include <systemc>
39
40namespace Gem5SystemC
41{
42
43// forward declerations
44class SCSlavePort;
45class SCMasterPort;
46
47class Gem5SimControlInterface : public sc_core::sc_interface
48{
49  public:
50    virtual SCSlavePort* getSlavePort(const std::string& name) = 0;
51    virtual SCMasterPort* getMasterPort(const std::string& name) = 0;
52};
53
54}
55
56#endif
57