tlm_master.py revision 12047 
1#
2# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31#
32# Authors: Christian Menard
33#
34
35import m5
36from m5.objects import *
37
38import os
39
40# Base System Architecture:
41#         +-----+           ^
42#         | TLM |           | TLM World
43#         +--+--+           | (see main.cc)
44#            |              v
45# +----------v-----------+  External Port (see sc_master_port.*)
46# |        Membus        |  ^
47# +----------+-----------+  |
48#            |              | gem5 World
49#        +---v----+         |
50#        | Memory |         |
51#        +--------+         v
52#
53
54# Create a system with a Crossbar and a simple Memory:
55system = System()
56system.membus = IOXBar(width = 16)
57system.physmem = SimpleMemory(range = AddrRange('512MB'))
58system.clk_domain = SrcClockDomain(clock = '1.5GHz',
59    voltage_domain = VoltageDomain(voltage = '1V'))
60
61# Create a external TLM port:
62system.tlm = ExternalMaster()
63system.tlm.port_type = "tlm_master"
64system.tlm.port_data = "transactor"
65
66# Route the connections:
67system.system_port = system.membus.slave
68system.physmem.port = system.membus.master
69system.tlm.port = system.membus.slave
70system.mem_mode = 'timing'
71
72# Start the simulation:
73root = Root(full_system = False, system = system)
74m5.instantiate()
75m5.simulate()
76