o3_stat_config.ini revision 9935:cc9dc514036e
1# Copyright (c) 2012 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Author: Dam Sunwoo 37# 38# Sample stats config file (O3CPU) for m5stats2streamline.py 39# 40# Stats grouped together will show as grouped in Streamline. 41# E.g., 42# 43# icache = 44# icache.overall_hits::total 45# icache.overall_misses::total 46# 47# will display the icache as a stacked line chart. 48# Charts will still be configurable in Streamline. 49 50[PER_CPU_STATS] 51# "system.cpu#." will automatically prepended for per-CPU stats 52 53icache = 54 icache.overall_hits::total 55 icache.overall_misses::total 56 57dcache = 58 dcache.overall_hits::total 59 dcache.overall_misses::total 60 61[PER_SWITCHCPU_STATS] 62# If starting from checkpoints, CPU stats will be kept in system.switch_cpus#. 63# structures. 64# "system.switch_cpus#" will automatically prepended for per-CPU stats. 65# Note: L1 caches and table walker caches will still be connected to 66# system.cpu#! 67 68commit_inst_count = 69 commit.committedInsts 70 commit.commitSquashedInsts 71 72cycles = 73 numCycles 74 idleCycles 75 76branch_mispredict = 77 commit.branchMispredicts 78 79itb = 80 itb.hits 81 itb.misses 82 83dtb = 84 dtb.hits 85 dtb.misses 86 87commit_inst_breakdown = 88 commit.loads 89 commit.membars 90 commit.branches 91 commit.fp_insts 92 commit.int_insts 93 94int_regfile = 95 int_regfile_reads 96 int_regfile_writes 97 98misc_regfile = 99 misc_regfile_reads 100 misc_regfile_writes 101 102rename_full = 103 rename.ROBFullEvents 104 rename.IQFullEvents 105 rename.LSQFullEvents 106 107[PER_L2_STATS] 108# Automatically adapts to how many l2 caches are in the system 109 110l2 = 111 overall_hits::total 112 overall_misses::total 113 114[OTHER_STATS] 115# Anything that doesn't belong to CPU or L2 caches 116 117physmem = 118 system.physmem.bytes_read::total 119 system.physmem.bytes_written::total 120