m5op_x86.S revision 12157:c27b548bad70
12929Sktlim@umich.edu/*
211504Sandreas.sandberg@arm.com * Copyright (c) 2003-2006 The Regents of The University of Michigan
311504Sandreas.sandberg@arm.com * All rights reserved.
411504Sandreas.sandberg@arm.com *
511504Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without
611504Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are
711504Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright
811504Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer;
911504Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright
1011504Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the
1111504Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution;
1211504Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its
1311504Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from
1411504Sandreas.sandberg@arm.com * this software without specific prior written permission.
152932Sktlim@umich.edu *
162929Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172929Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182929Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192929Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202929Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212929Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222929Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232929Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242929Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252929Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262929Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272929Sktlim@umich.edu *
282929Sktlim@umich.edu * Authors: Gabe Black
292929Sktlim@umich.edu *          Nathan Binkert
302929Sktlim@umich.edu *          Ali Saidi
312929Sktlim@umich.edu */
322929Sktlim@umich.edu
332929Sktlim@umich.edu#include <gem5/asm/generic/m5ops.h>
342929Sktlim@umich.edu
352929Sktlim@umich.edu#ifdef M5OP_ADDR
362929Sktlim@umich.edu/* Use the memory mapped m5op interface */
372929Sktlim@umich.edu#define TWO_BYTE_OP(name, number)         \
382929Sktlim@umich.edu        .globl name;                      \
392929Sktlim@umich.edu        .func name;                       \
402932Sktlim@umich.eduname:                                     \
412932Sktlim@umich.edu        mov m5_mem, %r11;                 \
422932Sktlim@umich.edu        mov $number, %rax;                \
4311504Sandreas.sandberg@arm.com        shl $8, %rax;                     \
442929Sktlim@umich.edu        mov 0(%r11, %rax, 1), %rax;       \
452929Sktlim@umich.edu        ret;                              \
4611504Sandreas.sandberg@arm.com        .endfunc;
4711504Sandreas.sandberg@arm.com
4811504Sandreas.sandberg@arm.com#else
4911504Sandreas.sandberg@arm.com/* Use the magic instruction based m5op interface. This does not work
5011504Sandreas.sandberg@arm.com * in virtualized environments.
5111504Sandreas.sandberg@arm.com */
5211504Sandreas.sandberg@arm.com
532929Sktlim@umich.edu#define TWO_BYTE_OP(name, number)         \
542929Sktlim@umich.edu        .globl name;                      \
552929Sktlim@umich.edu        .func name;                       \
568947Sandreas.hansson@arm.comname:                                     \
578947Sandreas.hansson@arm.com        .byte 0x0F, 0x04;                 \
588947Sandreas.hansson@arm.com        .word number;                     \
592929Sktlim@umich.edu        ret;                              \
602929Sktlim@umich.edu        .endfunc;
6111504Sandreas.sandberg@arm.com
6211504Sandreas.sandberg@arm.com#endif
6311504Sandreas.sandberg@arm.com
6411504Sandreas.sandberg@arm.comTWO_BYTE_OP(arm, M5OP_ARM)
6511504Sandreas.sandberg@arm.comTWO_BYTE_OP(quiesce, M5OP_QUIESCE)
6611504Sandreas.sandberg@arm.comTWO_BYTE_OP(quiesceNs, M5OP_QUIESCE_NS)
6711504Sandreas.sandberg@arm.comTWO_BYTE_OP(quiesceCycle, M5OP_QUIESCE_CYCLE)
682929Sktlim@umich.eduTWO_BYTE_OP(quiesceTime, M5OP_QUIESCE_TIME)
6911504Sandreas.sandberg@arm.comTWO_BYTE_OP(rpns, M5OP_RPNS)
7011504Sandreas.sandberg@arm.comTWO_BYTE_OP(m5_exit, M5OP_EXIT)
716007Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_fail, M5OP_FAIL)
726007Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_initparam, M5OP_INIT_PARAM)
7311504Sandreas.sandberg@arm.comTWO_BYTE_OP(m5_loadsymbol, M5OP_LOAD_SYMBOL)
742929Sktlim@umich.eduTWO_BYTE_OP(m5_reset_stats, M5OP_RESET_STATS)
752929Sktlim@umich.eduTWO_BYTE_OP(m5_dump_stats, M5OP_DUMP_STATS)
7611504Sandreas.sandberg@arm.comTWO_BYTE_OP(m5_dumpreset_stats, M5OP_DUMP_RESET_STATS)
776007Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_checkpoint, M5OP_CHECKPOINT)
786007Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_readfile, M5OP_READ_FILE)
799781Sandreas.hansson@arm.comTWO_BYTE_OP(m5_writefile, M5OP_WRITE_FILE)
806007Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_debugbreak, M5OP_DEBUG_BREAK)
8111504Sandreas.sandberg@arm.comTWO_BYTE_OP(m5_switchcpu, M5OP_SWITCH_CPU)
822929Sktlim@umich.eduTWO_BYTE_OP(m5_addsymbol, M5OP_ADD_SYMBOL)
832929Sktlim@umich.eduTWO_BYTE_OP(m5_panic, M5OP_PANIC)
8411504Sandreas.sandberg@arm.comTWO_BYTE_OP(m5_work_begin, M5OP_WORK_BEGIN)
8511504Sandreas.sandberg@arm.comTWO_BYTE_OP(m5_work_end, M5OP_WORK_END)
8611504Sandreas.sandberg@arm.comTWO_BYTE_OP(m5_togglesync, M5OP_DIST_TOGGLE_SYNC)
8711504Sandreas.sandberg@arm.com