m5op_arm.S revision 8987:a5add07e066c
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Nathan Binkert 41 * Ali Saidi 42 * Chander Sudanthi 43 */ 44.syntax unified 45#ifdef __thumb__ 46.thumb 47#endif 48 49#define m5_op 0xEE 50 51#include "m5ops.h" 52 53#ifdef __thumb__ 54#define INST(op, ra, rb, func) \ 55 .short (((op) << 8) | (func)); \ 56 .short (((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb)) 57/* m5ops m5func */ 58/* ra coproc 1 op=1 rb */ 59#else 60#define INST(op, ra, rb, func) \ 61 .long (((op) << 24) | ((func) << 16) | ((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb)) 62/* m5ops m5func ra coproc 1 op=1 rb */ 63#endif 64 65#define LEAF(func) \ 66 .globl func; \ 67func: 68 69#define RET \ 70 mov pc,lr 71 72#define END(func) \ 73 74#define SIMPLE_OP(_f, _o) \ 75 LEAF(_f) \ 76 _o; \ 77 RET; \ 78 END(_f) 79 80#define ARM INST(m5_op, 0, 0, arm_func) 81#define QUIESCE INST(m5_op, 0, 0, quiesce_func) 82#define QUIESCENS INST(m5_op, 0, 0, quiescens_func) 83#define QUIESCECYC INST(m5_op, 0, 0, quiescecycle_func) 84#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) 85#define RPNS INST(m5_op, 0, 0, rpns_func) 86#define WAKE_CPU INST(m5_op, 0, 0, wakecpu_func) 87#define M5EXIT INST(m5_op, 0, 0, exit_func) 88#define INITPARAM INST(m5_op, 0, 0, initparam_func) 89#define LOADSYMBOL INST(m5_op, 0, 0, loadsymbol_func) 90#define RESET_STATS INST(m5_op, 0, 0, resetstats_func) 91#define DUMP_STATS INST(m5_op, 0, 0, dumpstats_func) 92#define DUMPRST_STATS INST(m5_op, 0, 0, dumprststats_func) 93#define CHECKPOINT INST(m5_op, 0, 0, ckpt_func) 94#define READFILE INST(m5_op, 0, 0, readfile_func) 95#define WRITEFILE INST(m5_op, 0, 0, writefile_func) 96#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) 97#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) 98#define ADDSYMBOL INST(m5_op, 0, 0, addsymbol_func) 99#define PANIC INST(m5_op, 0, 0, panic_func) 100#define WORK_BEGIN INST(m5_op, 0, 0, work_begin_func) 101#define WORK_END INST(m5_op, 0, 0, work_end_func) 102 103#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func) 104#define AN_ESM INST(m5_op, an_esm, 0, annotate_func) 105#define AN_BEGIN INST(m5_op, an_begin, 0, annotate_func) 106#define AN_END INST(m5_op, an_end, 0, annotate_func) 107#define AN_Q INST(m5_op, an_q, 0, annotate_func) 108#define AN_RQ INST(m5_op, an_rq, 0, annotate_func) 109#define AN_DQ INST(m5_op, an_dq, 0, annotate_func) 110#define AN_WF INST(m5_op, an_wf, 0, annotate_func) 111#define AN_WE INST(m5_op, an_we, 0, annotate_func) 112#define AN_WS INST(m5_op, an_ws, 0, annotate_func) 113#define AN_SQ INST(m5_op, an_sq, 0, annotate_func) 114#define AN_AQ INST(m5_op, an_aq, 0, annotate_func) 115#define AN_PQ INST(m5_op, an_pq, 0, annotate_func) 116#define AN_L INST(m5_op, an_l, 0, annotate_func) 117#define AN_IDENTIFY INST(m5_op, an_identify, 0, annotate_func) 118#define AN_GETID INST(m5_op, an_getid, 0, annotate_func) 119 120.text 121 122SIMPLE_OP(arm, ARM) 123SIMPLE_OP(quiesce, QUIESCE) 124SIMPLE_OP(quiesceNs, QUIESCENS) 125SIMPLE_OP(quiesceCycle, QUIESCECYC) 126SIMPLE_OP(quiesceTime, QUIESCETIME) 127SIMPLE_OP(rpns, RPNS) 128SIMPLE_OP(wakeCPU, WAKE_CPU) 129SIMPLE_OP(m5_exit, M5EXIT) 130SIMPLE_OP(m5_initparam, INITPARAM) 131SIMPLE_OP(m5_loadsymbol, LOADSYMBOL) 132SIMPLE_OP(m5_reset_stats, RESET_STATS) 133SIMPLE_OP(m5_dump_stats, DUMP_STATS) 134SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS) 135SIMPLE_OP(m5_checkpoint, CHECKPOINT) 136SIMPLE_OP(m5_readfile, READFILE) 137SIMPLE_OP(m5_writefile, WRITEFILE) 138SIMPLE_OP(m5_debugbreak, DEBUGBREAK) 139SIMPLE_OP(m5_switchcpu, SWITCHCPU) 140SIMPLE_OP(m5_addsymbol, ADDSYMBOL) 141SIMPLE_OP(m5_panic, PANIC) 142SIMPLE_OP(m5_work_begin, WORK_BEGIN) 143SIMPLE_OP(m5_work_end, WORK_END) 144 145SIMPLE_OP(m5a_bsm, AN_BSM) 146SIMPLE_OP(m5a_esm, AN_ESM) 147SIMPLE_OP(m5a_begin, AN_BEGIN) 148SIMPLE_OP(m5a_end, AN_END) 149SIMPLE_OP(m5a_q, AN_Q) 150SIMPLE_OP(m5a_rq, AN_RQ) 151SIMPLE_OP(m5a_dq, AN_DQ) 152SIMPLE_OP(m5a_wf, AN_WF) 153SIMPLE_OP(m5a_we, AN_WE) 154SIMPLE_OP(m5a_ws, AN_WS) 155SIMPLE_OP(m5a_sq, AN_SQ) 156SIMPLE_OP(m5a_aq, AN_AQ) 157SIMPLE_OP(m5a_pq, AN_PQ) 158SIMPLE_OP(m5a_l, AN_L) 159SIMPLE_OP(m5a_identify, AN_IDENTIFY) 160SIMPLE_OP(m5a_getid, AN_GETID) 161 162