m5op_alpha.S revision 5951:960caa92210d
1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Ali Saidi 30 */ 31 32#define m5_op 0x01 33 34#include "m5ops.h" 35 36#define INST(op, ra, rb, func) \ 37 .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) 38 39#define LEAF(func) \ 40 .align 3; \ 41 .globl func; \ 42 .ent func; \ 43func: 44 45#define RET \ 46 ret ($26) 47 48#define END(func) \ 49 .end func 50 51#define SIMPLE_OP(_f, _o) \ 52 LEAF(_f) \ 53 _o; \ 54 RET; \ 55 END(_f) 56 57#define ARM(reg) INST(m5_op, reg, 0, arm_func) 58#define QUIESCE INST(m5_op, 0, 0, quiesce_func) 59#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func) 60#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func) 61#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) 62#define RPNS INST(m5_op, 0, 0, rpns_func) 63#define WAKE_CPU(r1) INST(m5_op, r1, 0, wakecpu_func) 64#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) 65#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) 66#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func) 67#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) 68#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) 69#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) 70#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) 71#define READFILE INST(m5_op, 0, 0, readfile_func) 72#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) 73#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) 74#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func) 75#define PANIC INST(m5_op, 0, 0, panic_func) 76 77#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func) 78#define AN_ESM INST(m5_op, an_esm, 0, annotate_func) 79#define AN_BEGIN INST(m5_op, an_begin, 0, annotate_func) 80#define AN_END INST(m5_op, an_end, 0, annotate_func) 81#define AN_Q INST(m5_op, an_q, 0, annotate_func) 82#define AN_RQ INST(m5_op, an_rq, 0, annotate_func) 83#define AN_DQ INST(m5_op, an_dq, 0, annotate_func) 84#define AN_WF INST(m5_op, an_wf, 0, annotate_func) 85#define AN_WE INST(m5_op, an_we, 0, annotate_func) 86#define AN_WS INST(m5_op, an_ws, 0, annotate_func) 87#define AN_SQ INST(m5_op, an_sq, 0, annotate_func) 88#define AN_AQ INST(m5_op, an_aq, 0, annotate_func) 89#define AN_PQ INST(m5_op, an_pq, 0, annotate_func) 90#define AN_L INST(m5_op, an_l, 0, annotate_func) 91#define AN_IDENTIFY INST(m5_op, an_identify, 0, annotate_func) 92#define AN_GETID INST(m5_op, an_getid, 0, annotate_func) 93 94 95 .set noreorder 96 97SIMPLE_OP(arm, ARM(16)) 98SIMPLE_OP(quiesce, QUIESCE) 99SIMPLE_OP(quiesceNs, QUIESCENS(16)) 100SIMPLE_OP(quiesceCycle, QUIESCECYC(16)) 101SIMPLE_OP(quiesceTime, QUIESCETIME) 102SIMPLE_OP(rpns, RPNS) 103SIMPLE_OP(wakeCPU, WAKE_CPU(16)) 104SIMPLE_OP(m5_exit, M5EXIT(16)) 105SIMPLE_OP(m5_initparam, INITPARAM(0)) 106SIMPLE_OP(m5_loadsymbol, LOADSYMBOL(0)) 107SIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17)) 108SIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17)) 109SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS(16, 17)) 110SIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17)) 111SIMPLE_OP(m5_readfile, READFILE) 112SIMPLE_OP(m5_debugbreak, DEBUGBREAK) 113SIMPLE_OP(m5_switchcpu, SWITCHCPU) 114SIMPLE_OP(m5_addsymbol, ADDSYMBOL(16, 17)) 115SIMPLE_OP(m5_panic, PANIC) 116 117SIMPLE_OP(m5a_bsm, AN_BSM) 118SIMPLE_OP(m5a_esm, AN_ESM) 119SIMPLE_OP(m5a_begin, AN_BEGIN) 120SIMPLE_OP(m5a_end, AN_END) 121SIMPLE_OP(m5a_q, AN_Q) 122SIMPLE_OP(m5a_rq, AN_RQ) 123SIMPLE_OP(m5a_dq, AN_DQ) 124SIMPLE_OP(m5a_wf, AN_WF) 125SIMPLE_OP(m5a_we, AN_WE) 126SIMPLE_OP(m5a_ws, AN_WS) 127SIMPLE_OP(m5a_sq, AN_SQ) 128SIMPLE_OP(m5a_aq, AN_AQ) 129SIMPLE_OP(m5a_pq, AN_PQ) 130SIMPLE_OP(m5a_l, AN_L) 131SIMPLE_OP(m5a_identify, AN_IDENTIFY) 132SIMPLE_OP(m5a_getid, AN_GETID) 133 134