dirty.S revision 12771:75508af5d8dc
1# See LICENSE for license details. 2 3#***************************************************************************** 4# dirty.S 5#----------------------------------------------------------------------------- 6# 7# Test VM referenced and dirty bits. 8# 9 10#include "riscv_test.h" 11#include "test_macros.h" 12 13RVTEST_RV64M 14RVTEST_CODE_BEGIN 15 16 # Turn on VM 17 li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39 18 la a1, page_table_1 19 srl a1, a1, RISCV_PGSHIFT 20 or a1, a1, a0 21 csrw sptbr, a1 22 sfence.vma 23 24 # Set up MPRV with MPP=S, so loads and stores use S-mode 25 li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV 26 csrs mstatus, a1 27 28 # Try a faulting store to make sure dirty bit is not set 29 li TESTNUM, 2 30 li t2, 1 31 sw t2, dummy - DRAM_BASE, a0 32 33 # Set SUM=1 so user memory access is permitted 34 li TESTNUM, 3 35 li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM 36 csrs mstatus, a1 37 38 # Make sure SUM=1 works 39 lw t0, dummy - DRAM_BASE 40 bnez t0, die 41 42 # Try a non-faulting store to make sure dirty bit is set 43 sw t2, dummy - DRAM_BASE, a0 44 45 # Make sure it succeeded 46 lw t0, dummy - DRAM_BASE 47 bne t0, t2, die 48 49 # Leave MPRV 50 li t0, MSTATUS_MPRV 51 csrc mstatus, t0 52 53 # Make sure D bit is set 54 lw t0, page_table_1 55 li a0, PTE_A | PTE_D 56 and t0, t0, a0 57 bne t0, a0, die 58 59 # Enter MPRV again 60 li t0, MSTATUS_MPRV 61 csrs mstatus, t0 62 63 # Make sure that superpage entries trap when PPN LSBs are set. 64 li TESTNUM, 4 65 lw a0, page_table_1 - DRAM_BASE 66 or a0, a0, 1 << PTE_PPN_SHIFT 67 sw a0, page_table_1 - DRAM_BASE, t0 68 sfence.vma 69 sw a0, page_table_1 - DRAM_BASE, t0 70 j die 71 72 RVTEST_PASS 73 74 TEST_PASSFAIL 75 76 .align 2 77 .global mtvec_handler 78mtvec_handler: 79 csrr t0, mcause 80 add t0, t0, -CAUSE_STORE_PAGE_FAULT 81 bnez t0, die 82 83 li t1, 2 84 bne TESTNUM, t1, 1f 85 # Make sure D bit is clear 86 lw t0, page_table_1 87 and t1, t0, PTE_D 88 bnez t1, die 89skip: 90 csrr t0, mepc 91 add t0, t0, 4 92 csrw mepc, t0 93 mret 94 951: 96 li t1, 3 97 bne TESTNUM, t1, 1f 98 # The implementation doesn't appear to set D bits in HW. 99 # Make sure the D bit really is clear. 100 lw t0, page_table_1 101 and t1, t0, PTE_D 102 bnez t1, die 103 # Set the D bit. 104 or t0, t0, PTE_D 105 sw t0, page_table_1, t1 106 sfence.vma 107 mret 108 1091: 110 li t1, 4 111 bne TESTNUM, t1, 1f 112 j pass 113 1141: 115die: 116 RVTEST_FAIL 117 118RVTEST_CODE_END 119 120 .data 121RVTEST_DATA_BEGIN 122 123 TEST_DATA 124 125.align 12 126page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A 127dummy: .dword 0 128 129RVTEST_DATA_END 130