112771Sqtt2@cornell.edugem5 Specifc RISC-V tests
212771Sqtt2@cornell.edu=========================
312771Sqtt2@cornell.edu
412771Sqtt2@cornell.eduAbout
512771Sqtt2@cornell.edu-----
612771Sqtt2@cornell.edu
712771Sqtt2@cornell.eduThis work provides assembly testing infrastructure including single-threaded
812771Sqtt2@cornell.eduand multi-threaded tests for RISC-V ISA in gem5. Each test targets an
912771Sqtt2@cornell.eduindividual RISC-V instruction or a Linux system call. This work targets
1012771Sqtt2@cornell.edusystem call emulation (SE) mode in gem5.
1112771Sqtt2@cornell.edu
1212771Sqtt2@cornell.eduThis work is based on the riscv-tests project.
1312771Sqtt2@cornell.edu
1412771Sqtt2@cornell.eduLink to the orignal riscv-tests projects can be found here:
1512771Sqtt2@cornell.edu  https://github.com/riscv/riscv-tests
1612771Sqtt2@cornell.edu
1712771Sqtt2@cornell.eduLink to the original riscv-tests project's LICENSE and README can be found
1812771Sqtt2@cornell.eduhere:
1912771Sqtt2@cornell.edu  https://github.com/riscv/riscv-tests/blob/master/LICENSE
2012771Sqtt2@cornell.edu  https://github.com/riscv/riscv-tests/blob/master/README.md
2112771Sqtt2@cornell.edu
2212771Sqtt2@cornell.eduSpecific commit ID that this work is based off:
2312771Sqtt2@cornell.edu  68cad7baf3ed0a4553fffd14726d24519ee1296a
2412771Sqtt2@cornell.edu
2512771Sqtt2@cornell.eduChanges from the orignal riscv-tests project
2612771Sqtt2@cornell.edu--------------------------------------------
2712771Sqtt2@cornell.edu
2812771Sqtt2@cornell.edu1. Only rv64 tests are imported into this work
2912771Sqtt2@cornell.edu
3012771Sqtt2@cornell.eduThe original project offers both rv64 and rv32 tests. Since the current
3112771Sqtt2@cornell.eduimplementation of RISC-V in gem5 is focused on its 64-bit version, only
3212771Sqtt2@cornell.edu64-bit tests (rv64) are imported from the original project. Future work
3312771Sqtt2@cornell.eduon 32-bit can easily integrate all 32-bit tests into gem5.
3412771Sqtt2@cornell.edu
3512771Sqtt2@cornell.edu2. New testing environment for gem5
3612771Sqtt2@cornell.edu
3712771Sqtt2@cornell.eduSince the original riscv-tests project is designed for bare-metal system (i.e.,
3812771Sqtt2@cornell.eduwithout OS support), it offers several environments to control how a test
3912771Sqtt2@cornell.eduinteracts with a host machine (to-host communication). However, in gem5 SE
4012771Sqtt2@cornell.edumode, gem5 emulates an OS, and there is no host machine. Therefore, we
4112771Sqtt2@cornell.edudeveloped a new testing environment called `ps` for gem5.
4212771Sqtt2@cornell.edu
4312771Sqtt2@cornell.eduThis testing environment uses system call `exit` to return test results as an
4412771Sqtt2@cornell.eduexit code of a particular test instead of writing them to a host machine. This
4512771Sqtt2@cornell.eduenvironment requires the testing platform to implement/emulate at least `exit`
4612771Sqtt2@cornell.edusystem call.
4712771Sqtt2@cornell.edu
4812771Sqtt2@cornell.edu3. Minimal threading library written in assembly (`isa/macros/mt`)
4912771Sqtt2@cornell.edu
5012771Sqtt2@cornell.eduTo simplify debugging multi-threading systems, we developed a minimal threading
5112771Sqtt2@cornell.edulibrary that supports very basic threading functionality including creating a
5212771Sqtt2@cornell.eduthread, exiting a thread, waiting for some thread(s) on a condition, and waking
5312771Sqtt2@cornell.eduup some thread(s).
5412771Sqtt2@cornell.edu
5512771Sqtt2@cornell.eduMulti-threaded tests can rely on this library to manage multiple threads.
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5712771Sqtt2@cornell.edu4. RISC-V AMO, LR, and SC instruction tests (`isa/rv64uamt`)
5812771Sqtt2@cornell.edu
5912771Sqtt2@cornell.eduThis is a set of assembly tests that target multi-core systems and test AMO
6012771Sqtt2@cornell.eduinstructions. This test set uses a minimal number of system calls (i.e., clone,
6112771Sqtt2@cornell.edummap, munmap and exit) to create and manage threads.  It does not use any
6212771Sqtt2@cornell.educomplex sleep/wakeup mechanism to manage and synchronize threads to avoid
6312771Sqtt2@cornell.eduadding extra unnecessary complexity. The major goal of this test set is to
6412771Sqtt2@cornell.edustress AMO instructions. Threads only synchronize at the end of their
6512771Sqtt2@cornell.eduexecution. The master thread does a spin-wait to wait for all threads to
6612771Sqtt2@cornell.educomplete before it checks final results.
6712771Sqtt2@cornell.edu
6812771Sqtt2@cornell.edu5. Thread-related system call tests (`isa/rv64samt`)
6912771Sqtt2@cornell.edu
7012771Sqtt2@cornell.eduThis is a set of assembly tests that target thread-related system calls and
7112771Sqtt2@cornell.eduthread wait/wakeup behaviors. This set reuses some of the tests in
7212771Sqtt2@cornell.edu`isa/rv64uamt` but uses more advanced futex system call operations to make
7312771Sqtt2@cornell.eduthreads wait and wake up in certain cases. This test set also checks functional
7412771Sqtt2@cornell.edubehaviors of threads after a wait/wakeup operation.
7512771Sqtt2@cornell.edu
7612771Sqtt2@cornell.eduHow to compile this test suite
7712771Sqtt2@cornell.edu------------------------------
7812771Sqtt2@cornell.edu
7912771Sqtt2@cornell.edu1. Install RISC-V GNU toolchain. Source code and instruction on how to install
8012771Sqtt2@cornell.eduit can be found here: https://github.com/riscv/riscv-gnu-toolchain
8112771Sqtt2@cornell.edu
8212771Sqtt2@cornell.edu2. Run `make`
8312771Sqtt2@cornell.edu
8412771Sqtt2@cornell.edu3. Test binaries are in `$GEM5/tests/test-progs/asmtest/bin/riscv/` ($GEM5 is
8512771Sqtt2@cornell.eduyour gem5 directory)
8612771Sqtt2@cornell.edu
8712771Sqtt2@cornell.eduHow to run all tests
8812771Sqtt2@cornell.edu--------------------
8912771Sqtt2@cornell.edu
9012771Sqtt2@cornell.edu1. Run `./run-tests.py`
9112771Sqtt2@cornell.edu
9212771Sqtt2@cornell.edu2. Test outputs are in ./test-summary.out
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