stats.txt revision 10827:7f5467f2f8b8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.250954 # Number of seconds simulated 4sim_ticks 250953957500 # Number of ticks simulated 5final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 582427 # Simulator instruction rate (inst/s) 8host_op_rate 976201 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1106694320 # Simulator tick rate (ticks/s) 10host_mem_usage 282016 # Number of bytes of host memory used 11host_seconds 226.76 # Real time elapsed on the host 12sim_insts 132071193 # Number of instructions simulated 13sim_ops 221363385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory 18system.physmem.bytes_read::total 303040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 34system.cpu.workload.num_syscalls 400 # Number of system calls 35system.cpu.numCycles 501907915 # number of cpu cycles simulated 36system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 37system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38system.cpu.committedInsts 132071193 # Number of instructions committed 39system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed 40system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses 41system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses 42system.cpu.num_func_calls 1595632 # number of times a function call or return occured 43system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls 44system.cpu.num_int_insts 219019986 # number of integer instructions 45system.cpu.num_fp_insts 2162459 # number of float instructions 46system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read 47system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written 48system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read 49system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written 50system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read 51system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written 52system.cpu.num_mem_refs 77165304 # number of memory refs 53system.cpu.num_load_insts 56649587 # Number of load instructions 54system.cpu.num_store_insts 20515717 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 56system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 12326938 # Number of branches fetched 60system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction 61system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction 62system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction 63system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction 64system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction 65system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction 66system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction 67system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction 68system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction 69system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction 70system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction 71system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction 72system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction 73system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction 74system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction 75system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction 76system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction 77system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction 78system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction 79system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction 80system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction 81system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction 82system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction 83system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction 84system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction 85system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction 86system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction 87system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction 90system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction 91system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 221363385 # Class of executed instruction 95system.cpu.dcache.tags.replacements 41 # number of replacements 96system.cpu.dcache.tags.tagsinuse 1363.457564 # Cycle average of tags in use 97system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. 98system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. 99system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. 100system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 101system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457564 # Average occupied blocks per requestor 102system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy 103system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 108system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id 109system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id 110system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id 111system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses 112system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses 113system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits 114system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits 115system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits 116system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits 117system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits 118system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits 119system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits 120system.cpu.dcache.overall_hits::total 77195831 # number of overall hits 121system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses 122system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses 123system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses 124system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses 125system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses 126system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses 127system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses 128system.cpu.dcache.overall_misses::total 1905 # number of overall misses 129system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles 130system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles 131system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles 132system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles 133system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles 134system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles 135system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles 136system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles 137system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) 138system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) 139system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 140system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 141system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses 142system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses 143system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses 144system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses 145system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses 146system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses 147system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses 148system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses 149system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 150system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 151system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 152system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses 153system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency 154system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency 155system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency 156system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency 157system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency 158system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency 159system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency 160system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency 161system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 162system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 163system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 165system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 167system.cpu.dcache.fast_writes 0 # number of fast writes performed 168system.cpu.dcache.cache_copies 0 # number of cache copies performed 169system.cpu.dcache.writebacks::writebacks 7 # number of writebacks 170system.cpu.dcache.writebacks::total 7 # number of writebacks 171system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses 172system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses 173system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses 175system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses 176system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses 177system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses 178system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses 179system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17202000 # number of ReadReq MSHR miss cycles 180system.cpu.dcache.ReadReq_mshr_miss_latency::total 17202000 # number of ReadReq MSHR miss cycles 181system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84297000 # number of WriteReq MSHR miss cycles 182system.cpu.dcache.WriteReq_mshr_miss_latency::total 84297000 # number of WriteReq MSHR miss cycles 183system.cpu.dcache.demand_mshr_miss_latency::cpu.data 101499000 # number of demand (read+write) MSHR miss cycles 184system.cpu.dcache.demand_mshr_miss_latency::total 101499000 # number of demand (read+write) MSHR miss cycles 185system.cpu.dcache.overall_mshr_miss_latency::cpu.data 101499000 # number of overall MSHR miss cycles 186system.cpu.dcache.overall_mshr_miss_latency::total 101499000 # number of overall MSHR miss cycles 187system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses 188system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses 189system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses 190system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses 191system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 192system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 193system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 194system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses 195system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587 # average ReadReq mshr miss latency 196system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587 # average ReadReq mshr miss latency 197system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091 # average WriteReq mshr miss latency 198system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091 # average WriteReq mshr miss latency 199system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency 200system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency 201system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency 202system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency 203system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 204system.cpu.icache.tags.replacements 2836 # number of replacements 205system.cpu.icache.tags.tagsinuse 1455.296636 # Cycle average of tags in use 206system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. 207system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. 208system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. 209system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 210system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296636 # Average occupied blocks per requestor 211system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy 212system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy 213system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id 214system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 215system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id 216system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id 217system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id 218system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id 219system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id 220system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses 221system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses 222system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits 223system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits 224system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits 225system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits 226system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits 227system.cpu.icache.overall_hits::total 173489673 # number of overall hits 228system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses 229system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses 230system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses 231system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses 232system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses 233system.cpu.icache.overall_misses::total 4694 # number of overall misses 234system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles 235system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles 236system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles 237system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles 238system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles 239system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles 240system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) 241system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) 242system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses 243system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses 244system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses 245system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses 246system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses 247system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses 248system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses 249system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 250system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses 251system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 252system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency 253system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency 254system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency 255system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency 256system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency 257system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency 258system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 259system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 260system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 261system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 262system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 263system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 264system.cpu.icache.fast_writes 0 # number of fast writes performed 265system.cpu.icache.cache_copies 0 # number of cache copies performed 266system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses 267system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses 268system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses 269system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses 270system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses 271system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses 272system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173278500 # number of ReadReq MSHR miss cycles 273system.cpu.icache.ReadReq_mshr_miss_latency::total 173278500 # number of ReadReq MSHR miss cycles 274system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173278500 # number of demand (read+write) MSHR miss cycles 275system.cpu.icache.demand_mshr_miss_latency::total 173278500 # number of demand (read+write) MSHR miss cycles 276system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173278500 # number of overall MSHR miss cycles 277system.cpu.icache.overall_mshr_miss_latency::total 173278500 # number of overall MSHR miss cycles 278system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses 279system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses 280system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 281system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 282system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 283system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 284system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36914.891351 # average ReadReq mshr miss latency 285system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36914.891351 # average ReadReq mshr miss latency 286system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency 287system.cpu.icache.demand_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency 288system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency 289system.cpu.icache.overall_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency 290system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 291system.cpu.l2cache.tags.replacements 0 # number of replacements 292system.cpu.l2cache.tags.tagsinuse 2058.178675 # Cycle average of tags in use 293system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. 294system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. 295system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. 296system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 297system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor 298system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978570 # Average occupied blocks per requestor 299system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178361 # Average occupied blocks per requestor 300system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy 301system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy 302system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy 303system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy 304system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id 305system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 306system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id 307system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id 308system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id 310system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id 311system.cpu.l2cache.tags.tag_accesses 57590 # Number of tag accesses 312system.cpu.l2cache.tags.data_accesses 57590 # Number of data accesses 313system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits 314system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits 315system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits 316system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits 317system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits 318system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits 319system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits 320system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits 321system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits 322system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits 323system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits 324system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits 325system.cpu.l2cache.overall_hits::total 1864 # number of overall hits 326system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses 327system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses 328system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses 329system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses 330system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses 331system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses 332system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses 333system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses 334system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses 335system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses 336system.cpu.l2cache.overall_misses::total 4735 # number of overall misses 337system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149117500 # number of ReadReq miss cycles 338system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16801500 # number of ReadReq miss cycles 339system.cpu.l2cache.ReadReq_miss_latency::total 165919000 # number of ReadReq miss cycles 340system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles 341system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles 342system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles 343system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles 344system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles 345system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles 346system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles 347system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles 348system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) 349system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) 350system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) 351system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) 352system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) 353system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) 354system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) 355system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses 356system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses 357system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses 358system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses 359system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses 360system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses 361system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses 362system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses 363system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses 364system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses 365system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses 366system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses 367system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses 368system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses 369system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses 370system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses 371system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses 372system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadReq miss latency 373system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500 # average ReadReq miss latency 374system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658 # average ReadReq miss latency 375system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency 376system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency 377system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency 378system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency 379system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency 380system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency 381system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency 382system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency 383system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 384system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 385system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 386system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 387system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 388system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 389system.cpu.l2cache.fast_writes 0 # number of fast writes performed 390system.cpu.l2cache.cache_copies 0 # number of cache copies performed 391system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses 392system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses 393system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses 394system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses 395system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses 396system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses 397system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses 398system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses 399system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses 400system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses 401system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses 402system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115020000 # number of ReadReq MSHR miss cycles 403system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12960000 # number of ReadReq MSHR miss cycles 404system.cpu.l2cache.ReadReq_mshr_miss_latency::total 127980000 # number of ReadReq MSHR miss cycles 405system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63787500 # number of ReadExReq MSHR miss cycles 406system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63787500 # number of ReadExReq MSHR miss cycles 407system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115020000 # number of demand (read+write) MSHR miss cycles 408system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76747500 # number of demand (read+write) MSHR miss cycles 409system.cpu.l2cache.demand_mshr_miss_latency::total 191767500 # number of demand (read+write) MSHR miss cycles 410system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115020000 # number of overall MSHR miss cycles 411system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76747500 # number of overall MSHR miss cycles 412system.cpu.l2cache.overall_mshr_miss_latency::total 191767500 # number of overall MSHR miss cycles 413system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses 414system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses 415system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses 416system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses 417system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses 418system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses 419system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses 420system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses 421system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses 422system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses 423system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses 424system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 425system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 426system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 427system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 428system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 429system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 430system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 431system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 432system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 433system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 434system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 435system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 436system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution 438system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution 441system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes) 442system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes) 443system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes) 444system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) 445system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) 447system.cpu.toL2Bus.snoops 0 # Total snoops (count) 448system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram 449system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 450system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::1 6606 100.00% 100.00% # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram 459system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) 460system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 461system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) 462system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 463system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) 464system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 465system.membus.trans_dist::ReadReq 3160 # Transaction distribution 466system.membus.trans_dist::ReadResp 3160 # Transaction distribution 467system.membus.trans_dist::ReadExReq 1575 # Transaction distribution 468system.membus.trans_dist::ReadExResp 1575 # Transaction distribution 469system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) 470system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) 471system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) 472system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) 473system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) 474system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) 475system.membus.snoops 0 # Total snoops (count) 476system.membus.snoop_fanout::samples 4735 # Request fanout histogram 477system.membus.snoop_fanout::mean 0 # Request fanout histogram 478system.membus.snoop_fanout::stdev 0 # Request fanout histogram 479system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 480system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram 481system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 482system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 483system.membus.snoop_fanout::min_value 0 # Request fanout histogram 484system.membus.snoop_fanout::max_value 0 # Request fanout histogram 485system.membus.snoop_fanout::total 4735 # Request fanout histogram 486system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks) 487system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 488system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks) 489system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 490 491---------- End Simulation Statistics ---------- 492