stats.txt revision 11955:1170d039b31e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270605 # Number of seconds simulated 4sim_ticks 270604702500 # Number of ticks simulated 5final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1830893 # Simulator instruction rate (inst/s) 8host_op_rate 1830895 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2561189341 # Simulator tick rate (ticks/s) 10host_mem_usage 255916 # Number of bytes of host memory used 11host_seconds 105.66 # Real time elapsed on the host 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 19system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 850717 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 372736 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1223453 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 850717 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 850717 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 850717 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 372736 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1223453 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.numSyscalls 401 # Number of system calls 36system.cpu.pwrStateResidencyTicks::ON 270604702500 # Cumulative time (in ticks) in various power states 37system.cpu.numCycles 541209405 # number of cpu cycles simulated 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 193444518 # Number of instructions committed 41system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 44system.cpu.num_func_calls 1957920 # number of times a function call or return occured 45system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 46system.cpu.num_int_insts 167974806 # number of integer instructions 47system.cpu.num_fp_insts 1970372 # number of float instructions 48system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 49system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 50system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 51system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 52system.cpu.num_mem_refs 76733958 # number of memory refs 53system.cpu.num_load_insts 57735091 # Number of load instructions 54system.cpu.num_store_insts 18998867 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 56system.cpu.num_busy_cycles 541209404.998000 # Number of busy cycles 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 15132745 # Number of branches fetched 60system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 61system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 62system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 63system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 64system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction 65system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction 66system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction 67system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction 68system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% # Class of executed instruction 69system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction 70system.cpu.op_class::FloatMisc 0 0.00% 60.33% # Class of executed instruction 71system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction 72system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction 73system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction 74system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction 75system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction 76system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction 77system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction 78system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction 79system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction 80system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction 81system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction 82system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction 83system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction 84system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction 85system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction 86system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction 87system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction 88system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction 89system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 90system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 91system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 92system.cpu.op_class::MemRead 56837780 29.38% 89.71% # Class of executed instruction 93system.cpu.op_class::MemWrite 18800854 9.72% 99.43% # Class of executed instruction 94system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% # Class of executed instruction 95system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% # Class of executed instruction 96system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 97system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 98system.cpu.op_class::total 193445773 # Class of executed instruction 99system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 100system.cpu.dcache.tags.replacements 2 # number of replacements 101system.cpu.dcache.tags.tagsinuse 1237.152973 # Cycle average of tags in use 102system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 103system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 104system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 105system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 106system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 # Average occupied blocks per requestor 107system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 # Average percentage of cache occupancy 108system.cpu.dcache.tags.occ_percent::total 0.302039 # Average percentage of cache occupancy 109system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 110system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 111system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 115system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 116system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 117system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses 118system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 119system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 120system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 121system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 122system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 123system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 124system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 125system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 126system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits 127system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits 128system.cpu.dcache.overall_hits::total 76709932 # number of overall hits 129system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 130system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses 131system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 132system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 133system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 134system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 135system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 136system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 137system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 138system.cpu.dcache.overall_misses::total 1575 # number of overall misses 139system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 # number of ReadReq miss cycles 140system.cpu.dcache.ReadReq_miss_latency::total 31375500 # number of ReadReq miss cycles 141system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 # number of WriteReq miss cycles 142system.cpu.dcache.WriteReq_miss_latency::total 67852000 # number of WriteReq miss cycles 143system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 # number of SwapReq miss cycles 144system.cpu.dcache.SwapReq_miss_latency::total 63000 # number of SwapReq miss cycles 145system.cpu.dcache.demand_miss_latency::cpu.data 99227500 # number of demand (read+write) miss cycles 146system.cpu.dcache.demand_miss_latency::total 99227500 # number of demand (read+write) miss cycles 147system.cpu.dcache.overall_miss_latency::cpu.data 99227500 # number of overall miss cycles 148system.cpu.dcache.overall_miss_latency::total 99227500 # number of overall miss cycles 149system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 150system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 151system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 152system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 153system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 154system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 155system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 156system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses 157system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses 158system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses 159system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses 160system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses 161system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 162system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 163system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 164system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 165system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 166system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 167system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 168system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses 169system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63003.012048 # average ReadReq miss latency 170system.cpu.dcache.ReadReq_avg_miss_latency::total 63003.012048 # average ReadReq miss latency 171system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000.928505 # average WriteReq miss latency 172system.cpu.dcache.WriteReq_avg_miss_latency::total 63000.928505 # average WriteReq miss latency 173system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 63000 # average SwapReq miss latency 174system.cpu.dcache.SwapReq_avg_miss_latency::total 63000 # average SwapReq miss latency 175system.cpu.dcache.demand_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency 176system.cpu.dcache.demand_avg_miss_latency::total 63001.587302 # average overall miss latency 177system.cpu.dcache.overall_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::total 63001.587302 # average overall miss latency 179system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 180system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 181system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 183system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 185system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 186system.cpu.dcache.writebacks::total 2 # number of writebacks 187system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 188system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 189system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 191system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 192system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 193system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 194system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 195system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 196system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses 197system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30877500 # number of ReadReq MSHR miss cycles 198system.cpu.dcache.ReadReq_mshr_miss_latency::total 30877500 # number of ReadReq MSHR miss cycles 199system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66775000 # number of WriteReq MSHR miss cycles 200system.cpu.dcache.WriteReq_mshr_miss_latency::total 66775000 # number of WriteReq MSHR miss cycles 201system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 62000 # number of SwapReq MSHR miss cycles 202system.cpu.dcache.SwapReq_mshr_miss_latency::total 62000 # number of SwapReq MSHR miss cycles 203system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97652500 # number of demand (read+write) MSHR miss cycles 204system.cpu.dcache.demand_mshr_miss_latency::total 97652500 # number of demand (read+write) MSHR miss cycles 205system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97652500 # number of overall MSHR miss cycles 206system.cpu.dcache.overall_mshr_miss_latency::total 97652500 # number of overall MSHR miss cycles 207system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 208system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 209system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 210system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 211system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 212system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 213system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 214system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 215system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 216system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses 217system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62003.012048 # average ReadReq mshr miss latency 218system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62003.012048 # average ReadReq mshr miss latency 219system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000.928505 # average WriteReq mshr miss latency 220system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000.928505 # average WriteReq mshr miss latency 221system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 62000 # average SwapReq mshr miss latency 222system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 62000 # average SwapReq mshr miss latency 223system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency 224system.cpu.dcache.demand_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency 225system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency 226system.cpu.dcache.overall_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency 227system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 228system.cpu.icache.tags.replacements 10362 # number of replacements 229system.cpu.icache.tags.tagsinuse 1591.520958 # Cycle average of tags in use 230system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 231system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 232system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 233system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 234system.cpu.icache.tags.occ_blocks::cpu.inst 1591.520958 # Average occupied blocks per requestor 235system.cpu.icache.tags.occ_percent::cpu.inst 0.777110 # Average percentage of cache occupancy 236system.cpu.icache.tags.occ_percent::total 0.777110 # Average percentage of cache occupancy 237system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 239system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 240system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 241system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 242system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 243system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 244system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 245system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses 246system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 247system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 248system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 249system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 250system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 251system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 252system.cpu.icache.overall_hits::total 193433248 # number of overall hits 253system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 254system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 255system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 256system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 257system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 258system.cpu.icache.overall_misses::total 12288 # number of overall misses 259system.cpu.icache.ReadReq_miss_latency::cpu.inst 339828000 # number of ReadReq miss cycles 260system.cpu.icache.ReadReq_miss_latency::total 339828000 # number of ReadReq miss cycles 261system.cpu.icache.demand_miss_latency::cpu.inst 339828000 # number of demand (read+write) miss cycles 262system.cpu.icache.demand_miss_latency::total 339828000 # number of demand (read+write) miss cycles 263system.cpu.icache.overall_miss_latency::cpu.inst 339828000 # number of overall miss cycles 264system.cpu.icache.overall_miss_latency::total 339828000 # number of overall miss cycles 265system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 266system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 267system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 268system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 269system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 270system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 271system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 272system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 273system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 274system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 275system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 276system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses 277system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27655.273438 # average ReadReq miss latency 278system.cpu.icache.ReadReq_avg_miss_latency::total 27655.273438 # average ReadReq miss latency 279system.cpu.icache.demand_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency 280system.cpu.icache.demand_avg_miss_latency::total 27655.273438 # average overall miss latency 281system.cpu.icache.overall_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency 282system.cpu.icache.overall_avg_miss_latency::total 27655.273438 # average overall miss latency 283system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 284system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 285system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 286system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 287system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 288system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 289system.cpu.icache.writebacks::writebacks 10362 # number of writebacks 290system.cpu.icache.writebacks::total 10362 # number of writebacks 291system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 292system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 293system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 294system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 295system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 296system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses 297system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 327540000 # number of ReadReq MSHR miss cycles 298system.cpu.icache.ReadReq_mshr_miss_latency::total 327540000 # number of ReadReq MSHR miss cycles 299system.cpu.icache.demand_mshr_miss_latency::cpu.inst 327540000 # number of demand (read+write) MSHR miss cycles 300system.cpu.icache.demand_mshr_miss_latency::total 327540000 # number of demand (read+write) MSHR miss cycles 301system.cpu.icache.overall_mshr_miss_latency::cpu.inst 327540000 # number of overall MSHR miss cycles 302system.cpu.icache.overall_mshr_miss_latency::total 327540000 # number of overall MSHR miss cycles 303system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 304system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 305system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 306system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 307system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 308system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 309system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26655.273438 # average ReadReq mshr miss latency 310system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26655.273438 # average ReadReq mshr miss latency 311system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency 312system.cpu.icache.demand_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency 313system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency 314system.cpu.icache.overall_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency 315system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 316system.cpu.l2cache.tags.replacements 0 # number of replacements 317system.cpu.l2cache.tags.tagsinuse 3512.345683 # Cycle average of tags in use 318system.cpu.l2cache.tags.total_refs 19055 # Total number of references to valid blocks. 319system.cpu.l2cache.tags.sampled_refs 5173 # Sample count of references to valid blocks. 320system.cpu.l2cache.tags.avg_refs 3.683549 # Average number of references to valid blocks. 321system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 322system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.192191 # Average occupied blocks per requestor 323system.cpu.l2cache.tags.occ_blocks::cpu.data 1237.153491 # Average occupied blocks per requestor 324system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069433 # Average percentage of cache occupancy 325system.cpu.l2cache.tags.occ_percent::cpu.data 0.037755 # Average percentage of cache occupancy 326system.cpu.l2cache.tags.occ_percent::total 0.107188 # Average percentage of cache occupancy 327system.cpu.l2cache.tags.occ_task_id_blocks::1024 5173 # Occupied blocks per task id 328system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 329system.cpu.l2cache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id 330system.cpu.l2cache.tags.age_task_id_blocks_1024::2 719 # Occupied blocks per task id 331system.cpu.l2cache.tags.age_task_id_blocks_1024::3 833 # Occupied blocks per task id 332system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3523 # Occupied blocks per task id 333system.cpu.l2cache.tags.occ_task_id_percent::1024 0.157867 # Percentage of cache occupancy per task id 334system.cpu.l2cache.tags.tag_accesses 198997 # Number of tag accesses 335system.cpu.l2cache.tags.data_accesses 198997 # Number of data accesses 336system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 337system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits 338system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits 339system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits 340system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits 341system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 342system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits 343system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 344system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits 345system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits 346system.cpu.l2cache.overall_hits::total 8691 # number of overall hits 347system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses 348system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses 349system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses 350system.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses 351system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses 352system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses 353system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 354system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 355system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 356system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 357system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 358system.cpu.l2cache.overall_misses::total 5173 # number of overall misses 359system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65220000 # number of ReadExReq miss cycles 360system.cpu.l2cache.ReadExReq_miss_latency::total 65220000 # number of ReadExReq miss cycles 361system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217646500 # number of ReadCleanReq miss cycles 362system.cpu.l2cache.ReadCleanReq_miss_latency::total 217646500 # number of ReadCleanReq miss cycles 363system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30130000 # number of ReadSharedReq miss cycles 364system.cpu.l2cache.ReadSharedReq_miss_latency::total 30130000 # number of ReadSharedReq miss cycles 365system.cpu.l2cache.demand_miss_latency::cpu.inst 217646500 # number of demand (read+write) miss cycles 366system.cpu.l2cache.demand_miss_latency::cpu.data 95350000 # number of demand (read+write) miss cycles 367system.cpu.l2cache.demand_miss_latency::total 312996500 # number of demand (read+write) miss cycles 368system.cpu.l2cache.overall_miss_latency::cpu.inst 217646500 # number of overall miss cycles 369system.cpu.l2cache.overall_miss_latency::cpu.data 95350000 # number of overall miss cycles 370system.cpu.l2cache.overall_miss_latency::total 312996500 # number of overall miss cycles 371system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) 372system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) 373system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) 374system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) 375system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 376system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 377system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) 378system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) 379system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) 380system.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) 381system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses 382system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses 383system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses 384system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses 385system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses 386system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses 387system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 388system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 389system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses 390system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses 391system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 392system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 393system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 394system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 395system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 396system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 397system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 398system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses 399system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.927644 # average ReadExReq miss latency 400system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.927644 # average ReadExReq miss latency 401system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60507.784265 # average ReadCleanReq miss latency 402system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60507.784265 # average ReadCleanReq miss latency 403system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.008032 # average ReadSharedReq miss latency 404system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.008032 # average ReadSharedReq miss latency 405system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency 406system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency 407system.cpu.l2cache.demand_avg_miss_latency::total 60505.799343 # average overall miss latency 408system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency 409system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency 410system.cpu.l2cache.overall_avg_miss_latency::total 60505.799343 # average overall miss latency 411system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 415system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 416system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 417system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 418system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 419system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses 420system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses 421system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses 422system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses 423system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 424system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 425system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 426system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 427system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 428system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses 429system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54440000 # number of ReadExReq MSHR miss cycles 430system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440000 # number of ReadExReq MSHR miss cycles 431system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181676500 # number of ReadCleanReq MSHR miss cycles 432system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181676500 # number of ReadCleanReq MSHR miss cycles 433system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25150000 # number of ReadSharedReq MSHR miss cycles 434system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25150000 # number of ReadSharedReq MSHR miss cycles 435system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181676500 # number of demand (read+write) MSHR miss cycles 436system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79590000 # number of demand (read+write) MSHR miss cycles 437system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 # number of demand (read+write) MSHR miss cycles 438system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 # number of overall MSHR miss cycles 439system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 # number of overall MSHR miss cycles 440system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 # number of overall MSHR miss cycles 441system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 442system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 443system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses 444system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses 445system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 446system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 447system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 448system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 449system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 450system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 451system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 452system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses 453system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 # average ReadExReq mshr miss latency 454system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 # average ReadExReq mshr miss latency 455system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 # average ReadCleanReq mshr miss latency 456system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 # average ReadCleanReq mshr miss latency 457system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 # average ReadSharedReq mshr miss latency 458system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 # average ReadSharedReq mshr miss latency 459system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency 460system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency 461system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency 462system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency 463system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency 464system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency 465system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 466system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 467system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 468system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 469system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 470system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 471system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 472system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 479system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) 480system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 481system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) 482system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) 483system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 484system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) 485system.cpu.toL2Bus.snoops 0 # Total snoops (count) 486system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 487system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram 498system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) 499system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 500system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 501system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 502system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 503system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 504system.membus.snoop_filter.tot_requests 5173 # Total number of requests made to the snoop filter. 505system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 506system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 507system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 508system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 509system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 510system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states 511system.membus.trans_dist::ReadResp 4095 # Transaction distribution 512system.membus.trans_dist::ReadExReq 1078 # Transaction distribution 513system.membus.trans_dist::ReadExResp 1078 # Transaction distribution 514system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution 515system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 516system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 517system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 518system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) 519system.membus.snoops 0 # Total snoops (count) 520system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 521system.membus.snoop_fanout::samples 5173 # Request fanout histogram 522system.membus.snoop_fanout::mean 0 # Request fanout histogram 523system.membus.snoop_fanout::stdev 0 # Request fanout histogram 524system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 525system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram 526system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 527system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 528system.membus.snoop_fanout::min_value 0 # Request fanout histogram 529system.membus.snoop_fanout::max_value 0 # Request fanout histogram 530system.membus.snoop_fanout::total 5173 # Request fanout histogram 531system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) 532system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 533system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) 534system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 535 536---------- End Simulation Statistics ---------- 537