stats.txt revision 10220
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270563 # Number of seconds simulated 4sim_ticks 270563082000 # Number of ticks simulated 5final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1069922 # Simulator instruction rate (inst/s) 8host_op_rate 1069924 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1496457293 # Simulator tick rate (ticks/s) 10host_mem_usage 278484 # Number of bytes of host memory used 11host_seconds 180.80 # Real time elapsed on the host 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 18system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) 32system.membus.throughput 1223641 # Throughput (bytes/s) 33system.membus.trans_dist::ReadReq 4095 # Transaction distribution 34system.membus.trans_dist::ReadResp 4095 # Transaction distribution 35system.membus.trans_dist::ReadExReq 1078 # Transaction distribution 36system.membus.trans_dist::ReadExResp 1078 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 331072 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 43system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 45system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.workload.num_syscalls 401 # Number of system calls 49system.cpu.numCycles 541126164 # number of cpu cycles simulated 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.committedInsts 193444518 # Number of instructions committed 53system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 54system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 55system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 56system.cpu.num_func_calls 1957920 # number of times a function call or return occured 57system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 58system.cpu.num_int_insts 167974806 # number of integer instructions 59system.cpu.num_fp_insts 1970372 # number of float instructions 60system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 61system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 62system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 63system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 64system.cpu.num_mem_refs 76733958 # number of memory refs 65system.cpu.num_load_insts 57735091 # Number of load instructions 66system.cpu.num_store_insts 18998867 # Number of store instructions 67system.cpu.num_idle_cycles 0 # Number of idle cycles 68system.cpu.num_busy_cycles 541126164 # Number of busy cycles 69system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 70system.cpu.idle_fraction 0 # Percentage of idle cycles 71system.cpu.Branches 15132745 # Number of branches fetched 72system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 73system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 74system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 75system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 76system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction 77system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction 78system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction 79system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction 80system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction 81system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction 82system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction 83system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction 84system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction 85system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction 86system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction 87system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction 88system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction 89system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction 90system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction 91system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction 92system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction 93system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction 94system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction 95system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction 96system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction 97system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction 98system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction 99system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 100system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 101system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 102system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 103system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 104system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 105system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 106system.cpu.op_class::total 193445773 # Class of executed instruction 107system.cpu.icache.tags.replacements 10362 # number of replacements 108system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use 109system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 110system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 111system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 112system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 113system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor 114system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy 115system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy 116system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 117system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 118system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 119system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 120system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 121system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 122system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 123system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 124system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses 125system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 126system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 127system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 128system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 129system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 130system.cpu.icache.overall_hits::total 193433248 # number of overall hits 131system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 132system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 133system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 134system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 135system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 136system.cpu.icache.overall_misses::total 12288 # number of overall misses 137system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles 138system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles 139system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles 140system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles 141system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles 142system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles 143system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 144system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 145system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 146system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 147system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 148system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 149system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 150system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 151system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 152system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 153system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 154system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses 155system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency 156system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency 157system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency 158system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency 159system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency 160system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency 161system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 162system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 163system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 164system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 165system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 167system.cpu.icache.fast_writes 0 # number of fast writes performed 168system.cpu.icache.cache_copies 0 # number of cache copies performed 169system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 170system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 171system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 172system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 173system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 174system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses 175system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles 176system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles 177system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles 178system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles 179system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles 180system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles 181system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 182system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 183system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 184system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 185system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 186system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 187system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency 188system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency 189system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency 190system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency 191system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency 192system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency 193system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 194system.cpu.l2cache.tags.replacements 0 # number of replacements 195system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use 196system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. 197system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 198system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. 199system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 200system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor 201system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor 202system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor 203system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 204system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy 205system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 206system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy 207system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id 208system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 209system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id 210system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id 211system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id 212system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id 213system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id 214system.cpu.l2cache.tags.tag_accesses 116103 # Number of tag accesses 215system.cpu.l2cache.tags.data_accesses 116103 # Number of data accesses 216system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits 217system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits 218system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits 219system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits 220system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 221system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits 222system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits 223system.cpu.l2cache.overall_hits::total 8691 # number of overall hits 224system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses 225system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 226system.cpu.l2cache.ReadReq_misses::total 4095 # number of ReadReq misses 227system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses 228system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses 229system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 230system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 231system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 232system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 233system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 234system.cpu.l2cache.overall_misses::total 5173 # number of overall misses 235system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187044000 # number of ReadReq miss cycles 236system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25896000 # number of ReadReq miss cycles 237system.cpu.l2cache.ReadReq_miss_latency::total 212940000 # number of ReadReq miss cycles 238system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56056000 # number of ReadExReq miss cycles 239system.cpu.l2cache.ReadExReq_miss_latency::total 56056000 # number of ReadExReq miss cycles 240system.cpu.l2cache.demand_miss_latency::cpu.inst 187044000 # number of demand (read+write) miss cycles 241system.cpu.l2cache.demand_miss_latency::cpu.data 81952000 # number of demand (read+write) miss cycles 242system.cpu.l2cache.demand_miss_latency::total 268996000 # number of demand (read+write) miss cycles 243system.cpu.l2cache.overall_miss_latency::cpu.inst 187044000 # number of overall miss cycles 244system.cpu.l2cache.overall_miss_latency::cpu.data 81952000 # number of overall miss cycles 245system.cpu.l2cache.overall_miss_latency::total 268996000 # number of overall miss cycles 246system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) 247system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) 248system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) 249system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) 250system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) 251system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 252system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 253system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses 254system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses 255system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses 256system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses 257system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses 258system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses 259system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses 260system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 261system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses 262system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 263system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 264system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 265system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 266system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 267system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 268system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 269system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses 270system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 271system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 272system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 273system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 274system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 275system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 276system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 277system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 278system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 279system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 280system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 281system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 287system.cpu.l2cache.fast_writes 0 # number of fast writes performed 288system.cpu.l2cache.cache_copies 0 # number of cache copies performed 289system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses 290system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 291system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses 292system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 293system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 294system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 295system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 296system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 297system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 298system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 299system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses 300system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles 301system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles 302system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles 303system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles 304system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles 305system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles 306system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles 307system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles 308system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles 309system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles 310system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles 311system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses 312system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 313system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses 314system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 315system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 316system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 317system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 318system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 319system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 320system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 321system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses 322system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 323system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 324system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 325system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 326system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 327system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 328system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 329system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 330system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 331system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 332system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 333system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 334system.cpu.dcache.tags.replacements 2 # number of replacements 335system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use 336system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 337system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 338system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 339system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 340system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor 341system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy 342system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy 343system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 344system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 345system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 346system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 347system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 348system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 349system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 350system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 351system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses 352system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 353system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 354system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 355system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 356system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 357system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 358system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 359system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits 360system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits 361system.cpu.dcache.overall_hits::total 76709932 # number of overall hits 362system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 363system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses 364system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 365system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 366system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 367system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 368system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 369system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 370system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 371system.cpu.dcache.overall_misses::total 1575 # number of overall misses 372system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles 373system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles 374system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles 375system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles 376system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles 377system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles 378system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles 379system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles 380system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles 381system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles 382system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 383system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 384system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 385system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 386system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 387system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 388system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 389system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses 390system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses 391system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses 392system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses 393system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses 394system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 395system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 396system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 397system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 398system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 399system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 400system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 401system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses 402system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 403system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 404system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 405system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 406system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency 407system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency 408system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 409system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 410system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 411system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 418system.cpu.dcache.fast_writes 0 # number of fast writes performed 419system.cpu.dcache.cache_copies 0 # number of cache copies performed 420system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 421system.cpu.dcache.writebacks::total 2 # number of writebacks 422system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 423system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 424system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 425system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 426system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 427system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 428system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 429system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 430system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 431system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses 432system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles 433system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles 434system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles 435system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles 436system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles 437system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles 438system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles 439system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles 440system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles 441system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles 442system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 443system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 444system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 445system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 446system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 447system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 448system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 449system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 450system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 451system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses 452system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 455system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 456system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency 457system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency 458system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 459system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 460system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 461system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 462system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 463system.cpu.toL2Bus.throughput 3279915 # Throughput (bytes/s) 464system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 469system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes) 472system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) 473system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) 475system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) 476system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 477system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks) 478system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 479system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 480system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 481system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 482system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 483 484---------- End Simulation Statistics ---------- 485