stats.txt revision 9838
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270563 # Number of seconds simulated 4sim_ticks 270563082000 # Number of ticks simulated 5final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 872463 # Simulator instruction rate (inst/s) 8host_op_rate 872464 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1220278409 # Simulator tick rate (ticks/s) 10host_mem_usage 236504 # Number of bytes of host memory used 11host_seconds 221.72 # Real time elapsed on the host 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 16system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) 30system.membus.throughput 1223641 # Throughput (bytes/s) 31system.membus.trans_dist::ReadReq 4095 # Transaction distribution 32system.membus.trans_dist::ReadResp 4095 # Transaction distribution 33system.membus.trans_dist::ReadExReq 1078 # Transaction distribution 34system.membus.trans_dist::ReadExResp 1078 # Transaction distribution 35system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 36system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 37system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 38system.membus.tot_pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) 39system.membus.data_through_bus 331072 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) 42system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 43system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) 44system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 45system.cpu.workload.num_syscalls 401 # Number of system calls 46system.cpu.numCycles 541126164 # number of cpu cycles simulated 47system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 48system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 49system.cpu.committedInsts 193444518 # Number of instructions committed 50system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 51system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 52system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 53system.cpu.num_func_calls 1957920 # number of times a function call or return occured 54system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 55system.cpu.num_int_insts 167974806 # number of integer instructions 56system.cpu.num_fp_insts 1970372 # number of float instructions 57system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 58system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 59system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 60system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 61system.cpu.num_mem_refs 76733958 # number of memory refs 62system.cpu.num_load_insts 57735091 # Number of load instructions 63system.cpu.num_store_insts 18998867 # Number of store instructions 64system.cpu.num_idle_cycles 0 # Number of idle cycles 65system.cpu.num_busy_cycles 541126164 # Number of busy cycles 66system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 67system.cpu.idle_fraction 0 # Percentage of idle cycles 68system.cpu.icache.tags.replacements 10362 # number of replacements 69system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use 70system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 71system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 72system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 73system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 74system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor 75system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy 76system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy 77system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 78system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 79system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 80system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 81system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 82system.cpu.icache.overall_hits::total 193433248 # number of overall hits 83system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 84system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 85system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 86system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 87system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 88system.cpu.icache.overall_misses::total 12288 # number of overall misses 89system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles 90system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles 91system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles 92system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles 93system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles 94system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles 95system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 96system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 97system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 98system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 99system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 100system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 101system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 102system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 103system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 104system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 105system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 106system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses 107system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency 108system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency 109system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency 110system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency 111system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency 112system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency 113system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 114system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 115system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 116system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 117system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 118system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119system.cpu.icache.fast_writes 0 # number of fast writes performed 120system.cpu.icache.cache_copies 0 # number of cache copies performed 121system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 122system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 123system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 124system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 125system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 126system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses 127system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles 128system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles 129system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles 130system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles 131system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles 132system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles 133system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 134system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 135system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 136system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 137system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 138system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 139system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency 140system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency 141system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency 142system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency 143system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency 144system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency 145system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 146system.cpu.l2cache.tags.replacements 0 # number of replacements 147system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use 148system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. 149system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 150system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. 151system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 152system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor 153system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor 154system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor 155system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 156system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy 157system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 158system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy 159system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits 160system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits 161system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits 162system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits 163system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 164system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits 165system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits 166system.cpu.l2cache.overall_hits::total 8691 # number of overall hits 167system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses 168system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 169system.cpu.l2cache.ReadReq_misses::total 4095 # number of ReadReq misses 170system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses 171system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses 172system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 173system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 174system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 175system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 176system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 177system.cpu.l2cache.overall_misses::total 5173 # number of overall misses 178system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187044000 # number of ReadReq miss cycles 179system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25896000 # number of ReadReq miss cycles 180system.cpu.l2cache.ReadReq_miss_latency::total 212940000 # number of ReadReq miss cycles 181system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56056000 # number of ReadExReq miss cycles 182system.cpu.l2cache.ReadExReq_miss_latency::total 56056000 # number of ReadExReq miss cycles 183system.cpu.l2cache.demand_miss_latency::cpu.inst 187044000 # number of demand (read+write) miss cycles 184system.cpu.l2cache.demand_miss_latency::cpu.data 81952000 # number of demand (read+write) miss cycles 185system.cpu.l2cache.demand_miss_latency::total 268996000 # number of demand (read+write) miss cycles 186system.cpu.l2cache.overall_miss_latency::cpu.inst 187044000 # number of overall miss cycles 187system.cpu.l2cache.overall_miss_latency::cpu.data 81952000 # number of overall miss cycles 188system.cpu.l2cache.overall_miss_latency::total 268996000 # number of overall miss cycles 189system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) 190system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) 191system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) 192system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) 193system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) 194system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 195system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 196system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses 197system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses 198system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses 199system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses 200system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses 201system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses 202system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses 203system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 204system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses 205system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 206system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 207system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 208system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 209system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 210system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 211system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 212system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses 213system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 214system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 215system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 216system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 217system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 218system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 219system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 220system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 221system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 222system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 223system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 224system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 225system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 226system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 227system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 228system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 229system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 230system.cpu.l2cache.fast_writes 0 # number of fast writes performed 231system.cpu.l2cache.cache_copies 0 # number of cache copies performed 232system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses 233system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 234system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses 235system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 236system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 237system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 238system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 239system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 240system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 241system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 242system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses 243system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles 244system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles 245system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles 246system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles 247system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles 248system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles 249system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles 250system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles 251system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles 252system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles 253system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles 254system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses 255system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 256system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses 257system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 258system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 259system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 260system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 261system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 262system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 263system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 264system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses 265system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 266system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 267system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 268system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 269system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 270system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 271system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 272system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 273system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 274system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 275system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 276system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 277system.cpu.dcache.tags.replacements 2 # number of replacements 278system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use 279system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 280system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 281system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 282system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 283system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor 284system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy 285system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy 286system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 287system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 288system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 289system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 290system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 291system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 292system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 293system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits 294system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits 295system.cpu.dcache.overall_hits::total 76709932 # number of overall hits 296system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 297system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses 298system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 299system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 300system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 301system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 302system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 303system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 304system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 305system.cpu.dcache.overall_misses::total 1575 # number of overall misses 306system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles 307system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles 308system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles 309system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles 310system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles 311system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles 312system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles 313system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles 314system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles 315system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles 316system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 317system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 318system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 319system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 320system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 321system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 322system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 323system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses 324system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses 325system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses 326system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses 327system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses 328system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 329system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 330system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 331system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 332system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 333system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 334system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 335system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses 336system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 337system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 338system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 339system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 340system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency 341system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency 342system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 343system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 344system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 345system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 346system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 347system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 348system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 349system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 350system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 351system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 352system.cpu.dcache.fast_writes 0 # number of fast writes performed 353system.cpu.dcache.cache_copies 0 # number of cache copies performed 354system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 355system.cpu.dcache.writebacks::total 2 # number of writebacks 356system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 357system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 358system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 359system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 360system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 361system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 362system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 363system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 364system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 365system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses 366system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles 367system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles 368system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles 369system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles 370system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles 371system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles 372system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles 373system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles 374system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles 375system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles 376system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 377system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 378system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 379system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 380system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 381system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 382system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 383system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 384system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 385system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses 386system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 387system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 388system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 389system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 390system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency 391system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency 392system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 393system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 394system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 395system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 396system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 397system.cpu.toL2Bus.throughput 3279915 # Throughput (bytes/s) 398system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution 399system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 400system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution 401system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 402system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 403system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes) 404system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 405system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes) 406system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) 407system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 408system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) 409system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) 410system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 411system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks) 412system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 413system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 414system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 415system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 416system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 417 418---------- End Simulation Statistics ---------- 419