stats.txt revision 9150
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270629 # Number of seconds simulated 4sim_ticks 270628667000 # Number of ticks simulated 5final_tick 270628667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1532509 # Simulator instruction rate (inst/s) 8host_op_rate 1532510 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2143977461 # Simulator tick rate (ticks/s) 10host_mem_usage 235212 # Number of bytes of host memory used 11host_seconds 126.23 # Real time elapsed on the host 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 16system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 850642 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 372703 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1223344 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 850642 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 850642 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 850642 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 372703 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1223344 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.workload.num_syscalls 401 # Number of system calls 31system.cpu.numCycles 541257334 # number of cpu cycles simulated 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.committedInsts 193444518 # Number of instructions committed 35system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 36system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 37system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 38system.cpu.num_func_calls 1957920 # number of times a function call or return occured 39system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 40system.cpu.num_int_insts 167974806 # number of integer instructions 41system.cpu.num_fp_insts 1970372 # number of float instructions 42system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 43system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 44system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 45system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 46system.cpu.num_mem_refs 76733958 # number of memory refs 47system.cpu.num_load_insts 57735091 # Number of load instructions 48system.cpu.num_store_insts 18998867 # Number of store instructions 49system.cpu.num_idle_cycles 0 # Number of idle cycles 50system.cpu.num_busy_cycles 541257334 # Number of busy cycles 51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 52system.cpu.idle_fraction 0 # Percentage of idle cycles 53system.cpu.icache.replacements 10362 # number of replacements 54system.cpu.icache.tagsinuse 1591.550018 # Cycle average of tags in use 55system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks. 56system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. 57system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks. 58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 59system.cpu.icache.occ_blocks::cpu.inst 1591.550018 # Average occupied blocks per requestor 60system.cpu.icache.occ_percent::cpu.inst 0.777124 # Average percentage of cache occupancy 61system.cpu.icache.occ_percent::total 0.777124 # Average percentage of cache occupancy 62system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 63system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 64system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 65system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 66system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 67system.cpu.icache.overall_hits::total 193433248 # number of overall hits 68system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 69system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 70system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 71system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 72system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 73system.cpu.icache.overall_misses::total 12288 # number of overall misses 74system.cpu.icache.ReadReq_miss_latency::cpu.inst 323106000 # number of ReadReq miss cycles 75system.cpu.icache.ReadReq_miss_latency::total 323106000 # number of ReadReq miss cycles 76system.cpu.icache.demand_miss_latency::cpu.inst 323106000 # number of demand (read+write) miss cycles 77system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles 78system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles 79system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles 80system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 81system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 82system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 83system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 84system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 85system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 86system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 87system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 88system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 89system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 90system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 91system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses 92system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency 93system.cpu.icache.ReadReq_avg_miss_latency::total 26294.433594 # average ReadReq miss latency 94system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency 95system.cpu.icache.demand_avg_miss_latency::total 26294.433594 # average overall miss latency 96system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency 97system.cpu.icache.overall_avg_miss_latency::total 26294.433594 # average overall miss latency 98system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 99system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 100system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 101system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 102system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 103system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104system.cpu.icache.fast_writes 0 # number of fast writes performed 105system.cpu.icache.cache_copies 0 # number of cache copies performed 106system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 107system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 108system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 109system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 110system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 111system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses 112system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles 113system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles 114system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles 115system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles 116system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles 117system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles 118system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 119system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 120system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 121system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 122system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 123system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency 125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency 126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency 127system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency 129system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency 130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 131system.cpu.dcache.replacements 2 # number of replacements 132system.cpu.dcache.tagsinuse 1237.179149 # Cycle average of tags in use 133system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks. 134system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. 135system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks. 136system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 137system.cpu.dcache.occ_blocks::cpu.data 1237.179149 # Average occupied blocks per requestor 138system.cpu.dcache.occ_percent::cpu.data 0.302046 # Average percentage of cache occupancy 139system.cpu.dcache.occ_percent::total 0.302046 # Average percentage of cache occupancy 140system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 141system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 142system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 143system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 144system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 145system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 146system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 147system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits 148system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits 149system.cpu.dcache.overall_hits::total 76709932 # number of overall hits 150system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 151system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses 152system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 153system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 154system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 155system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 156system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 157system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 158system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 159system.cpu.dcache.overall_misses::total 1575 # number of overall misses 160system.cpu.dcache.ReadReq_miss_latency::cpu.data 27888000 # number of ReadReq miss cycles 161system.cpu.dcache.ReadReq_miss_latency::total 27888000 # number of ReadReq miss cycles 162system.cpu.dcache.WriteReq_miss_latency::cpu.data 60312000 # number of WriteReq miss cycles 163system.cpu.dcache.WriteReq_miss_latency::total 60312000 # number of WriteReq miss cycles 164system.cpu.dcache.SwapReq_miss_latency::cpu.data 56000 # number of SwapReq miss cycles 165system.cpu.dcache.SwapReq_miss_latency::total 56000 # number of SwapReq miss cycles 166system.cpu.dcache.demand_miss_latency::cpu.data 88200000 # number of demand (read+write) miss cycles 167system.cpu.dcache.demand_miss_latency::total 88200000 # number of demand (read+write) miss cycles 168system.cpu.dcache.overall_miss_latency::cpu.data 88200000 # number of overall miss cycles 169system.cpu.dcache.overall_miss_latency::total 88200000 # number of overall miss cycles 170system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 171system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 172system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 173system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 175system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 176system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 177system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses 178system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses 179system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses 180system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses 181system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses 182system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 183system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 184system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 185system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 186system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 187system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 188system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 189system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses 190system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 191system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency 192system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 193system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency 194system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency 195system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency 196system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 197system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency 198system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 199system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency 200system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 201system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 202system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 203system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 204system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 205system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 206system.cpu.dcache.fast_writes 0 # number of fast writes performed 207system.cpu.dcache.cache_copies 0 # number of cache copies performed 208system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 209system.cpu.dcache.writebacks::total 2 # number of writebacks 210system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 211system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 212system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 213system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 214system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 215system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 216system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 217system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 218system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 219system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses 220system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles 221system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles 222system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles 223system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles 224system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles 225system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles 226system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles 227system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles 228system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles 229system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles 230system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 231system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 232system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 233system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 234system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 235system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 236system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 237system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 238system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 239system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses 240system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 241system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 242system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 243system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 244system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency 245system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency 246system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 247system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 248system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 249system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 250system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 251system.cpu.l2cache.replacements 0 # number of replacements 252system.cpu.l2cache.tagsinuse 2678.289604 # Cycle average of tags in use 253system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. 254system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. 255system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. 256system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 257system.cpu.l2cache.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor 258system.cpu.l2cache.occ_blocks::cpu.inst 2275.240623 # Average occupied blocks per requestor 259system.cpu.l2cache.occ_blocks::cpu.data 403.048526 # Average occupied blocks per requestor 260system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 261system.cpu.l2cache.occ_percent::cpu.inst 0.069435 # Average percentage of cache occupancy 262system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 263system.cpu.l2cache.occ_percent::total 0.081735 # Average percentage of cache occupancy 264system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits 265system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits 266system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits 267system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits 268system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 269system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits 270system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits 271system.cpu.l2cache.overall_hits::total 8691 # number of overall hits 272system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses 273system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 274system.cpu.l2cache.ReadReq_misses::total 4095 # number of ReadReq misses 275system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses 276system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses 277system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 278system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 279system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 280system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 281system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 282system.cpu.l2cache.overall_misses::total 5173 # number of overall misses 283system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187044000 # number of ReadReq miss cycles 284system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25896000 # number of ReadReq miss cycles 285system.cpu.l2cache.ReadReq_miss_latency::total 212940000 # number of ReadReq miss cycles 286system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56056000 # number of ReadExReq miss cycles 287system.cpu.l2cache.ReadExReq_miss_latency::total 56056000 # number of ReadExReq miss cycles 288system.cpu.l2cache.demand_miss_latency::cpu.inst 187044000 # number of demand (read+write) miss cycles 289system.cpu.l2cache.demand_miss_latency::cpu.data 81952000 # number of demand (read+write) miss cycles 290system.cpu.l2cache.demand_miss_latency::total 268996000 # number of demand (read+write) miss cycles 291system.cpu.l2cache.overall_miss_latency::cpu.inst 187044000 # number of overall miss cycles 292system.cpu.l2cache.overall_miss_latency::cpu.data 81952000 # number of overall miss cycles 293system.cpu.l2cache.overall_miss_latency::total 268996000 # number of overall miss cycles 294system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) 295system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) 296system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) 297system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) 298system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) 299system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 300system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 301system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses 302system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses 303system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses 304system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses 305system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses 306system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses 307system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses 308system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 309system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses 310system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 311system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 312system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 313system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 314system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 315system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 316system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 317system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses 318system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 319system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 320system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 321system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 322system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 323system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 324system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 325system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 326system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 327system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 328system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 329system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 330system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 331system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 332system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 333system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 334system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 335system.cpu.l2cache.fast_writes 0 # number of fast writes performed 336system.cpu.l2cache.cache_copies 0 # number of cache copies performed 337system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses 338system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 339system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses 340system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 341system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 342system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 343system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 344system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 345system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 346system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 347system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses 348system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles 349system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles 350system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles 351system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles 352system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles 353system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles 354system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles 355system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles 356system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles 357system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles 358system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles 359system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses 360system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 361system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses 362system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 363system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 364system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 365system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 366system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 367system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 368system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 369system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses 370system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 371system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 372system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 373system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 374system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 375system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 376system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 377system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 378system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 379system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 380system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 381system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 382 383---------- End Simulation Statistics ---------- 384