stats.txt revision 8348
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270577 # Number of seconds simulated 4sim_ticks 270576960000 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 1189238 # Simulator instruction rate (inst/s) 7host_tick_rate 1663421950 # Simulator tick rate (ticks/s) 8host_mem_usage 233652 # Number of bytes of host memory used 9host_seconds 162.66 # Real time elapsed on the host 10sim_insts 193444769 # Number of instructions simulated 11system.cpu.workload.num_syscalls 401 # Number of system calls 12system.cpu.numCycles 541153920 # number of cpu cycles simulated 13system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 14system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 15system.cpu.num_insts 193444769 # Number of instructions executed 16system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses 17system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 18system.cpu.num_func_calls 1957920 # number of times a function call or return occured 19system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls 20system.cpu.num_int_insts 167974818 # number of integer instructions 21system.cpu.num_fp_insts 1970372 # number of float instructions 22system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read 23system.cpu.num_int_register_writes 163703466 # number of times the integer registers were written 24system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 25system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 26system.cpu.num_mem_refs 76733959 # number of memory refs 27system.cpu.num_load_insts 57735092 # Number of load instructions 28system.cpu.num_store_insts 18998867 # Number of store instructions 29system.cpu.num_idle_cycles 0 # Number of idle cycles 30system.cpu.num_busy_cycles 541153920 # Number of busy cycles 31system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 32system.cpu.idle_fraction 0 # Percentage of idle cycles 33system.cpu.icache.replacements 10362 # number of replacements 34system.cpu.icache.tagsinuse 1591.571713 # Cycle average of tags in use 35system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. 36system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. 37system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. 38system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context 40system.cpu.icache.occ_percent::0 0.777135 # Average percentage of cache occupancy 41system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits 42system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits 43system.cpu.icache.overall_hits 193433261 # number of overall hits 44system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses 45system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses 46system.cpu.icache.overall_misses 12288 # number of overall misses 47system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles 48system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles 49system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles 50system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses) 51system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses 52system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses 53system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses 54system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses 55system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses 56system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency 57system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency 58system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency 59system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 60system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 61system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 62system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 63system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 64system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 65system.cpu.icache.fast_writes 0 # number of fast writes performed 66system.cpu.icache.cache_copies 0 # number of cache copies performed 67system.cpu.icache.writebacks 0 # number of writebacks 68system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 69system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 70system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses 71system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses 72system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses 73system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 74system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles 75system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles 76system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles 77system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 78system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses 79system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses 80system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses 81system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency 82system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency 83system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency 84system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 85system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 86system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 87system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 88system.cpu.dcache.replacements 2 # number of replacements 89system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use 90system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. 91system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. 92system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. 93system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 94system.cpu.dcache.occ_blocks::0 1237.197455 # Average occupied blocks per context 95system.cpu.dcache.occ_percent::0 0.302050 # Average percentage of cache occupancy 96system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits 97system.cpu.dcache.WriteReq_hits 18975362 # number of WriteReq hits 98system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits 99system.cpu.dcache.demand_hits 76709933 # number of demand (read+write) hits 100system.cpu.dcache.overall_hits 76709933 # number of overall hits 101system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses 102system.cpu.dcache.WriteReq_misses 1077 # number of WriteReq misses 103system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses 104system.cpu.dcache.demand_misses 1575 # number of demand (read+write) misses 105system.cpu.dcache.overall_misses 1575 # number of overall misses 106system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles 107system.cpu.dcache.WriteReq_miss_latency 60312000 # number of WriteReq miss cycles 108system.cpu.dcache.SwapReq_miss_latency 56000 # number of SwapReq miss cycles 109system.cpu.dcache.demand_miss_latency 88200000 # number of demand (read+write) miss cycles 110system.cpu.dcache.overall_miss_latency 88200000 # number of overall miss cycles 111system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) 112system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) 113system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) 114system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses 115system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses 116system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses 117system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses 118system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses 119system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses 120system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses 121system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency 122system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 123system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency 124system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency 125system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency 126system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 127system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 128system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 129system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 130system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 131system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 132system.cpu.dcache.fast_writes 0 # number of fast writes performed 133system.cpu.dcache.cache_copies 0 # number of cache copies performed 134system.cpu.dcache.writebacks 2 # number of writebacks 135system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 136system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 137system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses 138system.cpu.dcache.WriteReq_mshr_misses 1077 # number of WriteReq MSHR misses 139system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses 140system.cpu.dcache.demand_mshr_misses 1575 # number of demand (read+write) MSHR misses 141system.cpu.dcache.overall_mshr_misses 1575 # number of overall MSHR misses 142system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 143system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles 144system.cpu.dcache.WriteReq_mshr_miss_latency 57081000 # number of WriteReq MSHR miss cycles 145system.cpu.dcache.SwapReq_mshr_miss_latency 53000 # number of SwapReq MSHR miss cycles 146system.cpu.dcache.demand_mshr_miss_latency 83475000 # number of demand (read+write) MSHR miss cycles 147system.cpu.dcache.overall_mshr_miss_latency 83475000 # number of overall MSHR miss cycles 148system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 149system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses 150system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses 151system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses 152system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses 153system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses 154system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency 155system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 156system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency 157system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency 158system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency 159system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 160system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 161system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 162system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 163system.cpu.l2cache.replacements 0 # number of replacements 164system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use 165system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. 166system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. 167system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. 168system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 169system.cpu.l2cache.occ_blocks::0 2678.326682 # Average occupied blocks per context 170system.cpu.l2cache.occ_blocks::1 0.000454 # Average occupied blocks per context 171system.cpu.l2cache.occ_percent::0 0.081736 # Average percentage of cache occupancy 172system.cpu.l2cache.occ_percent::1 0.000000 # Average percentage of cache occupancy 173system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits 174system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits 175system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits 176system.cpu.l2cache.overall_hits 8691 # number of overall hits 177system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses 178system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses 179system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses 180system.cpu.l2cache.overall_misses 5173 # number of overall misses 181system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles 182system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles 183system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles 184system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles 185system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses) 186system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) 187system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses) 188system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses 189system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses 190system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses 191system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 192system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses 193system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses 194system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 195system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 196system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 197system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 198system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 199system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 200system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 201system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 202system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 203system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 204system.cpu.l2cache.fast_writes 0 # number of fast writes performed 205system.cpu.l2cache.cache_copies 0 # number of cache copies performed 206system.cpu.l2cache.writebacks 0 # number of writebacks 207system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 208system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 209system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses 210system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses 211system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses 212system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses 213system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 214system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles 215system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles 216system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles 217system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles 218system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 219system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses 220system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 221system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses 222system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses 223system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 224system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 225system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 226system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 227system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 228system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 229system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 230system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 231 232---------- End Simulation Statistics ---------- 233