stats.txt revision 4312
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 471554 # Simulator instruction rate (inst/s) 4host_mem_usage 155352 # Number of bytes of host memory used 5host_seconds 410.21 # Real time elapsed on the host 6host_tick_rate 766692 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 193435973 # Number of instructions simulated 9sim_seconds 0.000315 # Number of seconds simulated 10sim_ticks 314505003 # Number of ticks simulated 11system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) 12system.cpu.dcache.ReadReq_avg_miss_latency 3705.925703 # average ReadReq miss latency 13system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2705.925703 # average ReadReq mshr miss latency 14system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits 15system.cpu.dcache.ReadReq_miss_latency 1845551 # number of ReadReq miss cycles 16system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses 17system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses 18system.cpu.dcache.ReadReq_mshr_miss_latency 1347551 # number of ReadReq MSHR miss cycles 19system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses 20system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses 21system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) 22system.cpu.dcache.SwapReq_avg_miss_latency 3995 # average SwapReq miss latency 23system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2995 # average SwapReq mshr miss latency 24system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits 25system.cpu.dcache.SwapReq_miss_latency 3995 # number of SwapReq miss cycles 26system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses 27system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses 28system.cpu.dcache.SwapReq_mshr_miss_latency 2995 # number of SwapReq MSHR miss cycles 29system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses 30system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses 31system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) 32system.cpu.dcache.WriteReq_avg_miss_latency 3678.678637 # average WriteReq miss latency 33system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2678.678637 # average WriteReq mshr miss latency 34system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits 35system.cpu.dcache.WriteReq_miss_latency 3995045 # number of WriteReq miss cycles 36system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses 37system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses 38system.cpu.dcache.WriteReq_mshr_miss_latency 2909045 # number of WriteReq MSHR miss cycles 39system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses 40system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses 41system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 42system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 43system.cpu.dcache.avg_refs 48410.960883 # Average number of references to valid blocks. 44system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 45system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked 46system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 47system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 48system.cpu.dcache.cache_copies 0 # number of cache copies performed 49system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses 50system.cpu.dcache.demand_avg_miss_latency 3687.244949 # average overall miss latency 51system.cpu.dcache.demand_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency 52system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits 53system.cpu.dcache.demand_miss_latency 5840596 # number of demand (read+write) miss cycles 54system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses 55system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses 56system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 57system.cpu.dcache.demand_mshr_miss_latency 4256596 # number of demand (read+write) MSHR miss cycles 58system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses 59system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses 60system.cpu.dcache.fast_writes 0 # number of fast writes performed 61system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 62system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 63system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses 64system.cpu.dcache.overall_avg_miss_latency 3687.244949 # average overall miss latency 65system.cpu.dcache.overall_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency 66system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 67system.cpu.dcache.overall_hits 76708968 # number of overall hits 68system.cpu.dcache.overall_miss_latency 5840596 # number of overall miss cycles 69system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses 70system.cpu.dcache.overall_misses 1584 # number of overall misses 71system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 72system.cpu.dcache.overall_mshr_miss_latency 4256596 # number of overall MSHR miss cycles 73system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses 74system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses 75system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 76system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 77system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 78system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 79system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 80system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 81system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 82system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 83system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 84system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 85system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 86system.cpu.dcache.replacements 26 # number of replacements 87system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. 88system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 89system.cpu.dcache.tagsinuse 1216.403972 # Cycle average of tags in use 90system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. 91system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 92system.cpu.dcache.writebacks 23 # number of writebacks 93system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) 94system.cpu.icache.ReadReq_avg_miss_latency 3138.680633 # average ReadReq miss latency 95system.cpu.icache.ReadReq_avg_mshr_miss_latency 2138.680633 # average ReadReq mshr miss latency 96system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits 97system.cpu.icache.ReadReq_miss_latency 38505334 # number of ReadReq miss cycles 98system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses 99system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses 100system.cpu.icache.ReadReq_mshr_miss_latency 26237334 # number of ReadReq MSHR miss cycles 101system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses 102system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses 103system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 104system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 105system.cpu.icache.avg_refs 15766.523150 # Average number of references to valid blocks. 106system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked 107system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked 108system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 109system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 110system.cpu.icache.cache_copies 0 # number of cache copies performed 111system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses 112system.cpu.icache.demand_avg_miss_latency 3138.680633 # average overall miss latency 113system.cpu.icache.demand_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency 114system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits 115system.cpu.icache.demand_miss_latency 38505334 # number of demand (read+write) miss cycles 116system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses 117system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses 118system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 119system.cpu.icache.demand_mshr_miss_latency 26237334 # number of demand (read+write) MSHR miss cycles 120system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses 121system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses 122system.cpu.icache.fast_writes 0 # number of fast writes performed 123system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 124system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 125system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses 126system.cpu.icache.overall_avg_miss_latency 3138.680633 # average overall miss latency 127system.cpu.icache.overall_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency 128system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 129system.cpu.icache.overall_hits 193423706 # number of overall hits 130system.cpu.icache.overall_miss_latency 38505334 # number of overall miss cycles 131system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses 132system.cpu.icache.overall_misses 12268 # number of overall misses 133system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 134system.cpu.icache.overall_mshr_miss_latency 26237334 # number of overall MSHR miss cycles 135system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses 136system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses 137system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 138system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 139system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 140system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 141system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 142system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 143system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 144system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 145system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 146system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 147system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 148system.cpu.icache.replacements 10342 # number of replacements 149system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. 150system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 151system.cpu.icache.tagsinuse 1567.271345 # Cycle average of tags in use 152system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. 153system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 154system.cpu.icache.writebacks 0 # number of writebacks 155system.cpu.idle_fraction 0 # Percentage of idle cycles 156system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses) 157system.cpu.l2cache.ReadReq_avg_miss_latency 2847.598413 # average ReadReq miss latency 158system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1846.400619 # average ReadReq mshr miss latency 159system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits 160system.cpu.l2cache.ReadReq_miss_latency 14713541 # number of ReadReq miss cycles 161system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses 162system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses 163system.cpu.l2cache.ReadReq_mshr_miss_latency 9540352 # number of ReadReq MSHR miss cycles 164system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses 165system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses 166system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) 167system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits 168system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 169system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 170system.cpu.l2cache.avg_refs 1.685311 # Average number of references to valid blocks. 171system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked 172system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked 173system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 174system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked 175system.cpu.l2cache.cache_copies 0 # number of cache copies performed 176system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses 177system.cpu.l2cache.demand_avg_miss_latency 2847.598413 # average overall miss latency 178system.cpu.l2cache.demand_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency 179system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits 180system.cpu.l2cache.demand_miss_latency 14713541 # number of demand (read+write) miss cycles 181system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses 182system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses 183system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 184system.cpu.l2cache.demand_mshr_miss_latency 9540352 # number of demand (read+write) MSHR miss cycles 185system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses 186system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses 187system.cpu.l2cache.fast_writes 0 # number of fast writes performed 188system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 189system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 190system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses 191system.cpu.l2cache.overall_avg_miss_latency 2847.598413 # average overall miss latency 192system.cpu.l2cache.overall_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency 193system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 194system.cpu.l2cache.overall_hits 8708 # number of overall hits 195system.cpu.l2cache.overall_miss_latency 14713541 # number of overall miss cycles 196system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses 197system.cpu.l2cache.overall_misses 5167 # number of overall misses 198system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 199system.cpu.l2cache.overall_mshr_miss_latency 9540352 # number of overall MSHR miss cycles 200system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses 201system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses 202system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 203system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 204system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 205system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 206system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 207system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 208system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 209system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 210system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 211system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 212system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 213system.cpu.l2cache.replacements 0 # number of replacements 214system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks. 215system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 216system.cpu.l2cache.tagsinuse 3448.701925 # Cycle average of tags in use 217system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks. 218system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 219system.cpu.l2cache.writebacks 0 # number of writebacks 220system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 221system.cpu.numCycles 314505003 # number of cpu cycles simulated 222system.cpu.num_insts 193435973 # Number of instructions executed 223system.cpu.num_refs 76732959 # Number of memory references 224system.cpu.workload.PROG:num_syscalls 396 # Number of system calls 225 226---------- End Simulation Statistics ---------- 227