stats.txt revision 11369
14312SN/A 24312SN/A---------- Begin Simulation Statistics ---------- 311201Sandreas.hansson@arm.comsim_seconds 0.270600 # Number of seconds simulated 411201Sandreas.hansson@arm.comsim_ticks 270599529500 # Number of ticks simulated 511201Sandreas.hansson@arm.comfinal_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68348SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711312Santhony.gutierrez@amd.comhost_inst_rate 568132 # Simulator instruction rate (inst/s) 811312Santhony.gutierrez@amd.comhost_op_rate 568133 # Simulator op (including micro ops) rate (op/s) 911312Santhony.gutierrez@amd.comhost_tick_rate 794730164 # Simulator tick rate (ticks/s) 1011312Santhony.gutierrez@amd.comhost_mem_usage 235264 # Number of bytes of host memory used 1111312Santhony.gutierrez@amd.comhost_seconds 340.49 # Real time elapsed on the host 129150SN/Asim_insts 193444518 # Number of instructions simulated 139150SN/Asim_ops 193444756 # Number of ops (including micro ops) simulated 1410036SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 169055SN/Asystem.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 179055SN/Asystem.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 189055SN/Asystem.physmem.bytes_read::total 331072 # Number of bytes read from this memory 199055SN/Asystem.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 209055SN/Asystem.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 219055SN/Asystem.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 229055SN/Asystem.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 239055SN/Asystem.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 2411201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) 2511201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) 2611201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) 2711201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) 2811201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) 2911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) 3011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) 3111201Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) 3210036SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 338348SN/Asystem.cpu.workload.num_syscalls 401 # Number of system calls 3411201Sandreas.hansson@arm.comsystem.cpu.numCycles 541199059 # number of cpu cycles simulated 358348SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 368348SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 379150SN/Asystem.cpu.committedInsts 193444518 # Number of instructions committed 389150SN/Asystem.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 399150SN/Asystem.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 408348SN/Asystem.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 418348SN/Asystem.cpu.num_func_calls 1957920 # number of times a function call or return occured 429150SN/Asystem.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 439150SN/Asystem.cpu.num_int_insts 167974806 # number of integer instructions 448348SN/Asystem.cpu.num_fp_insts 1970372 # number of float instructions 459150SN/Asystem.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 469150SN/Asystem.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 478348SN/Asystem.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 488348SN/Asystem.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 499150SN/Asystem.cpu.num_mem_refs 76733958 # number of memory refs 509150SN/Asystem.cpu.num_load_insts 57735091 # Number of load instructions 518348SN/Asystem.cpu.num_store_insts 18998867 # Number of store instructions 5210488SN/Asystem.cpu.num_idle_cycles 0.002000 # Number of idle cycles 5311201Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles 5410488SN/Asystem.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 5510488SN/Asystem.cpu.idle_fraction 0.000000 # Percentage of idle cycles 5610063SN/Asystem.cpu.Branches 15132745 # Number of branches fetched 5710220SN/Asystem.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 5810220SN/Asystem.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 5910220SN/Asystem.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 6010220SN/Asystem.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 6110220SN/Asystem.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction 6210220SN/Asystem.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction 6310220SN/Asystem.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction 6410220SN/Asystem.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction 6510220SN/Asystem.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction 6610220SN/Asystem.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction 6710220SN/Asystem.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction 6810220SN/Asystem.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction 6910220SN/Asystem.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction 7010220SN/Asystem.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction 7110220SN/Asystem.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction 7210220SN/Asystem.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction 7310220SN/Asystem.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction 7410220SN/Asystem.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction 7510220SN/Asystem.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction 7610220SN/Asystem.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction 7710220SN/Asystem.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction 7810220SN/Asystem.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction 7910220SN/Asystem.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction 8010220SN/Asystem.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction 8110220SN/Asystem.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction 8210220SN/Asystem.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction 8310220SN/Asystem.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction 8410220SN/Asystem.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 8510220SN/Asystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 8610220SN/Asystem.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 8710220SN/Asystem.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 8810220SN/Asystem.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 8910220SN/Asystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 9010220SN/Asystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 9110220SN/Asystem.cpu.op_class::total 193445773 # Class of executed instruction 929838SN/Asystem.cpu.dcache.tags.replacements 2 # number of replacements 9311201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use 949838SN/Asystem.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 959838SN/Asystem.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 969838SN/Asystem.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 979838SN/Asystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 9811201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor 9911201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy 10011201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy 10110036SN/Asystem.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 10210036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 10310036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 10410036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 10510036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 10610036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 10710036SN/Asystem.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 10810036SN/Asystem.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 10910036SN/Asystem.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses 1109481SN/Asystem.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 1119481SN/Asystem.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 1129481SN/Asystem.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 1139481SN/Asystem.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 1149481SN/Asystem.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 1159481SN/Asystem.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 1169481SN/Asystem.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 1179481SN/Asystem.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits 1189481SN/Asystem.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits 1199481SN/Asystem.cpu.dcache.overall_hits::total 76709932 # number of overall hits 1209481SN/Asystem.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 1219481SN/Asystem.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses 1229481SN/Asystem.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 1239481SN/Asystem.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 1249481SN/Asystem.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 1259481SN/Asystem.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 1269481SN/Asystem.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 1279481SN/Asystem.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 1289481SN/Asystem.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 1299481SN/Asystem.cpu.dcache.overall_misses::total 1575 # number of overall misses 13011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles 13111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles 13211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles 13311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles 13411201Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles 13511201Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles 13611201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles 13711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles 13811201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles 13911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles 1409481SN/Asystem.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 1419481SN/Asystem.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 1429481SN/Asystem.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 1439481SN/Asystem.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 1449481SN/Asystem.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 1459481SN/Asystem.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 1469481SN/Asystem.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 1479481SN/Asystem.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses 1489481SN/Asystem.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses 1499481SN/Asystem.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses 1509481SN/Asystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses 1519481SN/Asystem.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses 1529481SN/Asystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 1539481SN/Asystem.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 1549481SN/Asystem.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 1559481SN/Asystem.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 1569481SN/Asystem.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 1579481SN/Asystem.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 1589481SN/Asystem.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 1599481SN/Asystem.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses 16011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency 16111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency 16211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency 16311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency 16411201Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency 16511201Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency 16611201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 16711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency 16811201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 16911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency 1709481SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1719481SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1729481SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1739481SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1749481SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1759481SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1769481SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 1779481SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 1789481SN/Asystem.cpu.dcache.writebacks::writebacks 2 # number of writebacks 1799481SN/Asystem.cpu.dcache.writebacks::total 2 # number of writebacks 1809481SN/Asystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 1819481SN/Asystem.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 1829481SN/Asystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 1839481SN/Asystem.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 1849481SN/Asystem.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 1859481SN/Asystem.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 1869481SN/Asystem.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 1879481SN/Asystem.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 1889481SN/Asystem.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 1899481SN/Asystem.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses 19011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles 19111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles 19211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles 19311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles 19411201Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles 19511201Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles 19611201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles 19711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles 19811201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles 19911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles 2009481SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 2019481SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 2029481SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 2039481SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 2049481SN/Asystem.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 2059481SN/Asystem.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 2069481SN/Asystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 2079481SN/Asystem.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 2089481SN/Asystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 2099481SN/Asystem.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses 21011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency 21111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency 21211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency 21311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency 21411201Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency 21511201Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency 21611201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 21711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 21811201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 21911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 2209481SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 22110726SN/Asystem.cpu.icache.tags.replacements 10362 # number of replacements 22211201Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use 22310726SN/Asystem.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 22410726SN/Asystem.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 22510726SN/Asystem.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 22610726SN/Asystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 22711201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor 22811201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy 22911201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy 23010726SN/Asystem.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 23110726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 23210726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 23310726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 23410726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 23510726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 23610726SN/Asystem.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 23710726SN/Asystem.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 23810726SN/Asystem.cpu.icache.tags.data_accesses 386903360 # Number of data accesses 23910726SN/Asystem.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 24010726SN/Asystem.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 24110726SN/Asystem.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 24210726SN/Asystem.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 24310726SN/Asystem.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 24410726SN/Asystem.cpu.icache.overall_hits::total 193433248 # number of overall hits 24510726SN/Asystem.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 24610726SN/Asystem.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 24710726SN/Asystem.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 24810726SN/Asystem.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 24910726SN/Asystem.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 25010726SN/Asystem.cpu.icache.overall_misses::total 12288 # number of overall misses 25111201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles 25211201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles 25311201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles 25411201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles 25511201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles 25611201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles 25710726SN/Asystem.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 25810726SN/Asystem.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 25910726SN/Asystem.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 26010726SN/Asystem.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 26110726SN/Asystem.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 26210726SN/Asystem.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 26310726SN/Asystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 26410726SN/Asystem.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 26510726SN/Asystem.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 26610726SN/Asystem.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 26710726SN/Asystem.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 26810726SN/Asystem.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses 26911201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency 27011201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency 27111201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 27211201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency 27311201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 27411201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency 27510726SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 27610726SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 27710726SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 27810726SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 27910726SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 28010726SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 28110726SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 28210726SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 28311201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 10362 # number of writebacks 28411201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 10362 # number of writebacks 28510726SN/Asystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 28610726SN/Asystem.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 28710726SN/Asystem.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 28810726SN/Asystem.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 28910726SN/Asystem.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 29010726SN/Asystem.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses 29111201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles 29211201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles 29311201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles 29411201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles 29511201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles 29611201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles 29710726SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 29810726SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 29910726SN/Asystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 30010726SN/Asystem.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 30110726SN/Asystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 30210726SN/Asystem.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 30311201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency 30411201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency 30511201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 30611201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 30711201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 30811201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 30910726SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 31010726SN/Asystem.cpu.l2cache.tags.replacements 0 # number of replacements 31111201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use 31210892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 31310726SN/Asystem.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 31410892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 31510726SN/Asystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 31611201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor 31711201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor 31811201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor 31910726SN/Asystem.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 32011201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy 32110726SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 32211201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy 32310726SN/Asystem.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id 32410726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 32510726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id 32610726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id 32710726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id 32810726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id 32910726SN/Asystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id 33010892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses 33110892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses 33211201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits 33311201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits 33411201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits 33511201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits 33610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 33710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits 33810726SN/Asystem.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 33910726SN/Asystem.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits 34010726SN/Asystem.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits 34110726SN/Asystem.cpu.l2cache.overall_hits::total 8691 # number of overall hits 34210726SN/Asystem.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses 34310726SN/Asystem.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses 34410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses 34510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses 34610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses 34710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses 34810726SN/Asystem.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 34910726SN/Asystem.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 35010726SN/Asystem.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 35110726SN/Asystem.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 35210726SN/Asystem.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 35310726SN/Asystem.cpu.l2cache.overall_misses::total 5173 # number of overall misses 35411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles 35511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles 35611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles 35711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles 35811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles 35911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles 36011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles 36111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles 36211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles 36311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles 36411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles 36511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles 36611201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) 36711201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) 36811201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) 36911201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) 37010726SN/Asystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 37110726SN/Asystem.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 37210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) 37310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) 37410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) 37510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) 37610726SN/Asystem.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses 37710726SN/Asystem.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses 37810726SN/Asystem.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses 37910726SN/Asystem.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses 38010726SN/Asystem.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses 38110726SN/Asystem.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses 38210726SN/Asystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 38310726SN/Asystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 38410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses 38510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses 38610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 38710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 38810726SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 38910726SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 39010726SN/Asystem.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 39110726SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 39210726SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 39310726SN/Asystem.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses 39411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency 39511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency 39611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency 39711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency 39811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency 39911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency 40011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency 40111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 40211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency 40311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency 40411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 40511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency 40610726SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 40710726SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 40810726SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 40910726SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 41010726SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 41110726SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 41210726SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 41310726SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 41410726SN/Asystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 41510726SN/Asystem.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 41610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses 41710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses 41810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses 41910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses 42010726SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 42110726SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 42210726SN/Asystem.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 42310726SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 42410726SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 42510726SN/Asystem.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses 42611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles 42711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles 42811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles 42911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles 43011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles 43111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles 43211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles 43311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles 43411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles 43511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles 43611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles 43711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles 43810726SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 43910726SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 44010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses 44110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses 44210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 44310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 44410726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 44510726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 44610726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 44710726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 44810726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 44910726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses 45011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency 45111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency 45211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency 45311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency 45411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency 45511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency 45611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 45711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 45811201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 45911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 46011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 46111201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 46210726SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 46311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 46411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 46511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 46611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 46711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 46811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 4699729SN/Asystem.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 47011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution 47111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution 4729729SN/Asystem.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 4739729SN/Asystem.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 47410892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 47510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 47610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) 4779838SN/Asystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 47810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) 47911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) 48010409SN/Asystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 48111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) 48210409SN/Asystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 48311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram 48411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram 48511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram 48610409SN/Asystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 48711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram 48811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram 48910409SN/Asystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 49010409SN/Asystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 49111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 49210409SN/Asystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 49311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram 49411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) 4959729SN/Asystem.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 4969729SN/Asystem.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 4979729SN/Asystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 4989729SN/Asystem.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 4999729SN/Asystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 50010726SN/Asystem.membus.trans_dist::ReadResp 4095 # Transaction distribution 50110726SN/Asystem.membus.trans_dist::ReadExReq 1078 # Transaction distribution 50210726SN/Asystem.membus.trans_dist::ReadExResp 1078 # Transaction distribution 50310892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution 50410726SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 50510726SN/Asystem.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 50610726SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 50710726SN/Asystem.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) 50810726SN/Asystem.membus.snoops 0 # Total snoops (count) 50910726SN/Asystem.membus.snoop_fanout::samples 5173 # Request fanout histogram 51010726SN/Asystem.membus.snoop_fanout::mean 0 # Request fanout histogram 51110726SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 51210726SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 51310726SN/Asystem.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram 51410726SN/Asystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 51510726SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 51610726SN/Asystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 51710726SN/Asystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 51810726SN/Asystem.membus.snoop_fanout::total 5173 # Request fanout histogram 51911201Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) 52010726SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 52111201Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) 52210726SN/Asystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 5234312SN/A 5244312SN/A---------- End Simulation Statistics ---------- 525