stats.txt revision 10892
14312SN/A 24312SN/A---------- Begin Simulation Statistics ---------- 39285SN/Asim_seconds 0.270563 # Number of seconds simulated 410726SN/Asim_ticks 270563082500 # Number of ticks simulated 510726SN/Afinal_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68348SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710892Sandreas.hansson@arm.comhost_inst_rate 1293394 # Simulator instruction rate (inst/s) 810892Sandreas.hansson@arm.comhost_op_rate 1293395 # Simulator op (including micro ops) rate (op/s) 910892Sandreas.hansson@arm.comhost_tick_rate 1809017316 # Simulator tick rate (ticks/s) 1010892Sandreas.hansson@arm.comhost_mem_usage 297764 # Number of bytes of host memory used 1110892Sandreas.hansson@arm.comhost_seconds 149.56 # Real time elapsed on the host 129150SN/Asim_insts 193444518 # Number of instructions simulated 139150SN/Asim_ops 193444756 # Number of ops (including micro ops) simulated 1410036SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 169055SN/Asystem.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 179055SN/Asystem.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 189055SN/Asystem.physmem.bytes_read::total 331072 # Number of bytes read from this memory 199055SN/Asystem.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 209055SN/Asystem.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 219055SN/Asystem.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 229055SN/Asystem.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 239055SN/Asystem.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 249285SN/Asystem.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s) 259285SN/Asystem.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s) 269285SN/Asystem.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) 279285SN/Asystem.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) 289285SN/Asystem.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) 299285SN/Asystem.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) 309285SN/Asystem.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) 319285SN/Asystem.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) 3210036SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 338348SN/Asystem.cpu.workload.num_syscalls 401 # Number of system calls 3410726SN/Asystem.cpu.numCycles 541126165 # number of cpu cycles simulated 358348SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 368348SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 379150SN/Asystem.cpu.committedInsts 193444518 # Number of instructions committed 389150SN/Asystem.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 399150SN/Asystem.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 408348SN/Asystem.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 418348SN/Asystem.cpu.num_func_calls 1957920 # number of times a function call or return occured 429150SN/Asystem.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 439150SN/Asystem.cpu.num_int_insts 167974806 # number of integer instructions 448348SN/Asystem.cpu.num_fp_insts 1970372 # number of float instructions 459150SN/Asystem.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 469150SN/Asystem.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 478348SN/Asystem.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 488348SN/Asystem.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 499150SN/Asystem.cpu.num_mem_refs 76733958 # number of memory refs 509150SN/Asystem.cpu.num_load_insts 57735091 # Number of load instructions 518348SN/Asystem.cpu.num_store_insts 18998867 # Number of store instructions 5210488SN/Asystem.cpu.num_idle_cycles 0.002000 # Number of idle cycles 5310726SN/Asystem.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles 5410488SN/Asystem.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 5510488SN/Asystem.cpu.idle_fraction 0.000000 # Percentage of idle cycles 5610063SN/Asystem.cpu.Branches 15132745 # Number of branches fetched 5710220SN/Asystem.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 5810220SN/Asystem.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 5910220SN/Asystem.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 6010220SN/Asystem.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 6110220SN/Asystem.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction 6210220SN/Asystem.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction 6310220SN/Asystem.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction 6410220SN/Asystem.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction 6510220SN/Asystem.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction 6610220SN/Asystem.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction 6710220SN/Asystem.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction 6810220SN/Asystem.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction 6910220SN/Asystem.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction 7010220SN/Asystem.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction 7110220SN/Asystem.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction 7210220SN/Asystem.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction 7310220SN/Asystem.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction 7410220SN/Asystem.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction 7510220SN/Asystem.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction 7610220SN/Asystem.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction 7710220SN/Asystem.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction 7810220SN/Asystem.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction 7910220SN/Asystem.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction 8010220SN/Asystem.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction 8110220SN/Asystem.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction 8210220SN/Asystem.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction 8310220SN/Asystem.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction 8410220SN/Asystem.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 8510220SN/Asystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 8610220SN/Asystem.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 8710220SN/Asystem.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 8810220SN/Asystem.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 8910220SN/Asystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 9010220SN/Asystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 9110220SN/Asystem.cpu.op_class::total 193445773 # Class of executed instruction 929838SN/Asystem.cpu.dcache.tags.replacements 2 # number of replacements 9310892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 1237.203933 # Cycle average of tags in use 949838SN/Asystem.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 959838SN/Asystem.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 969838SN/Asystem.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 979838SN/Asystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 9810892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 1237.203933 # Average occupied blocks per requestor 999838SN/Asystem.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy 1009838SN/Asystem.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy 10110036SN/Asystem.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 10210036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 10310036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 10410036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 10510036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 10610036SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 10710036SN/Asystem.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 10810036SN/Asystem.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 10910036SN/Asystem.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses 1109481SN/Asystem.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 1119481SN/Asystem.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 1129481SN/Asystem.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 1139481SN/Asystem.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 1149481SN/Asystem.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 1159481SN/Asystem.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 1169481SN/Asystem.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 1179481SN/Asystem.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits 1189481SN/Asystem.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits 1199481SN/Asystem.cpu.dcache.overall_hits::total 76709932 # number of overall hits 1209481SN/Asystem.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 1219481SN/Asystem.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses 1229481SN/Asystem.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 1239481SN/Asystem.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 1249481SN/Asystem.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 1259481SN/Asystem.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 1269481SN/Asystem.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 1279481SN/Asystem.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 1289481SN/Asystem.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 1299481SN/Asystem.cpu.dcache.overall_misses::total 1575 # number of overall misses 1309481SN/Asystem.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles 1319481SN/Asystem.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles 1329481SN/Asystem.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles 1339481SN/Asystem.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles 1349481SN/Asystem.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles 1359481SN/Asystem.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles 1369481SN/Asystem.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles 1379481SN/Asystem.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles 1389481SN/Asystem.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles 1399481SN/Asystem.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles 1409481SN/Asystem.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 1419481SN/Asystem.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 1429481SN/Asystem.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 1439481SN/Asystem.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 1449481SN/Asystem.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 1459481SN/Asystem.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 1469481SN/Asystem.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 1479481SN/Asystem.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses 1489481SN/Asystem.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses 1499481SN/Asystem.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses 1509481SN/Asystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses 1519481SN/Asystem.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses 1529481SN/Asystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 1539481SN/Asystem.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 1549481SN/Asystem.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 1559481SN/Asystem.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 1569481SN/Asystem.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 1579481SN/Asystem.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 1589481SN/Asystem.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 1599481SN/Asystem.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses 1609481SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 1619481SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 1629481SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 1639481SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 1649481SN/Asystem.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency 1659481SN/Asystem.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency 1669481SN/Asystem.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 1679481SN/Asystem.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 1689481SN/Asystem.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 1699481SN/Asystem.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 1709481SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1719481SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1729481SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1739481SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1749481SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1759481SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1769481SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 1779481SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 1789481SN/Asystem.cpu.dcache.writebacks::writebacks 2 # number of writebacks 1799481SN/Asystem.cpu.dcache.writebacks::total 2 # number of writebacks 1809481SN/Asystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 1819481SN/Asystem.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 1829481SN/Asystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 1839481SN/Asystem.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 1849481SN/Asystem.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 1859481SN/Asystem.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 1869481SN/Asystem.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 1879481SN/Asystem.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 1889481SN/Asystem.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 1899481SN/Asystem.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses 19010892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26892000 # number of ReadReq MSHR miss cycles 19110892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 26892000 # number of ReadReq MSHR miss cycles 19210892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58158000 # number of WriteReq MSHR miss cycles 19310892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 58158000 # number of WriteReq MSHR miss cycles 19410892Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 54000 # number of SwapReq MSHR miss cycles 19510892Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_mshr_miss_latency::total 54000 # number of SwapReq MSHR miss cycles 19610892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 85050000 # number of demand (read+write) MSHR miss cycles 19710892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 85050000 # number of demand (read+write) MSHR miss cycles 19810892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 85050000 # number of overall MSHR miss cycles 19910892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 85050000 # number of overall MSHR miss cycles 2009481SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 2019481SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 2029481SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 2039481SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 2049481SN/Asystem.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 2059481SN/Asystem.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 2069481SN/Asystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 2079481SN/Asystem.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 2089481SN/Asystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 2099481SN/Asystem.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses 21010892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency 21110892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency 21210892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 21310892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency 21410892Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 54000 # average SwapReq mshr miss latency 21510892Sandreas.hansson@arm.comsystem.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 54000 # average SwapReq mshr miss latency 21610892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 21710892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 21810892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 21910892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 2209481SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 22110726SN/Asystem.cpu.icache.tags.replacements 10362 # number of replacements 22210892Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 1591.579161 # Cycle average of tags in use 22310726SN/Asystem.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 22410726SN/Asystem.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 22510726SN/Asystem.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 22610726SN/Asystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 22710892Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1591.579161 # Average occupied blocks per requestor 22810726SN/Asystem.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy 22910726SN/Asystem.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy 23010726SN/Asystem.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 23110726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 23210726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 23310726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 23410726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 23510726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 23610726SN/Asystem.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 23710726SN/Asystem.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 23810726SN/Asystem.cpu.icache.tags.data_accesses 386903360 # Number of data accesses 23910726SN/Asystem.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 24010726SN/Asystem.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 24110726SN/Asystem.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 24210726SN/Asystem.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 24310726SN/Asystem.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 24410726SN/Asystem.cpu.icache.overall_hits::total 193433248 # number of overall hits 24510726SN/Asystem.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 24610726SN/Asystem.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 24710726SN/Asystem.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 24810726SN/Asystem.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 24910726SN/Asystem.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 25010726SN/Asystem.cpu.icache.overall_misses::total 12288 # number of overall misses 25110726SN/Asystem.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles 25210726SN/Asystem.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles 25310726SN/Asystem.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles 25410726SN/Asystem.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles 25510726SN/Asystem.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles 25610726SN/Asystem.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles 25710726SN/Asystem.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 25810726SN/Asystem.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 25910726SN/Asystem.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 26010726SN/Asystem.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 26110726SN/Asystem.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 26210726SN/Asystem.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 26310726SN/Asystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 26410726SN/Asystem.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 26510726SN/Asystem.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 26610726SN/Asystem.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 26710726SN/Asystem.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 26810726SN/Asystem.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses 26910726SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency 27010726SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency 27110726SN/Asystem.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency 27210726SN/Asystem.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency 27310726SN/Asystem.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency 27410726SN/Asystem.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency 27510726SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 27610726SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 27710726SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 27810726SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 27910726SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 28010726SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 28110726SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 28210726SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 28310726SN/Asystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 28410726SN/Asystem.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 28510726SN/Asystem.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 28610726SN/Asystem.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 28710726SN/Asystem.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 28810726SN/Asystem.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses 28910892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298530500 # number of ReadReq MSHR miss cycles 29010892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 298530500 # number of ReadReq MSHR miss cycles 29110892Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 298530500 # number of demand (read+write) MSHR miss cycles 29210892Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 298530500 # number of demand (read+write) MSHR miss cycles 29310892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 298530500 # number of overall MSHR miss cycles 29410892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 298530500 # number of overall MSHR miss cycles 29510726SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 29610726SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 29710726SN/Asystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 29810726SN/Asystem.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 29910726SN/Asystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 30010726SN/Asystem.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 30110892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.474284 # average ReadReq mshr miss latency 30210892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.474284 # average ReadReq mshr miss latency 30310892Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency 30410892Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency 30510892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency 30610892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency 30710726SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 30810726SN/Asystem.cpu.l2cache.tags.replacements 0 # number of replacements 30910892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 2678.340822 # Cycle average of tags in use 31010892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 31110726SN/Asystem.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 31210892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 31310726SN/Asystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 31410726SN/Asystem.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor 31510892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282887 # Average occupied blocks per requestor 31610892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 403.057483 # Average occupied blocks per requestor 31710726SN/Asystem.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 31810726SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy 31910726SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 32010726SN/Asystem.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy 32110726SN/Asystem.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id 32210726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 32310726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id 32410726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id 32510726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id 32610726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id 32710726SN/Asystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id 32810892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses 32910892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses 33010726SN/Asystem.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits 33110726SN/Asystem.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits 33210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 33310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits 33410726SN/Asystem.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 33510726SN/Asystem.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits 33610726SN/Asystem.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits 33710726SN/Asystem.cpu.l2cache.overall_hits::total 8691 # number of overall hits 33810726SN/Asystem.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses 33910726SN/Asystem.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses 34010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses 34110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses 34210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses 34310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses 34410726SN/Asystem.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 34510726SN/Asystem.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 34610726SN/Asystem.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 34710726SN/Asystem.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 34810726SN/Asystem.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 34910726SN/Asystem.cpu.l2cache.overall_misses::total 5173 # number of overall misses 35010726SN/Asystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles 35110726SN/Asystem.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles 35210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 188843000 # number of ReadCleanReq miss cycles 35310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 188843000 # number of ReadCleanReq miss cycles 35410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 26145000 # number of ReadSharedReq miss cycles 35510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 26145000 # number of ReadSharedReq miss cycles 35610726SN/Asystem.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles 35710726SN/Asystem.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles 35810726SN/Asystem.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles 35910726SN/Asystem.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles 36010726SN/Asystem.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles 36110726SN/Asystem.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles 36210726SN/Asystem.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) 36310726SN/Asystem.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) 36410726SN/Asystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 36510726SN/Asystem.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 36610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) 36710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) 36810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) 36910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) 37010726SN/Asystem.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses 37110726SN/Asystem.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses 37210726SN/Asystem.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses 37310726SN/Asystem.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses 37410726SN/Asystem.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses 37510726SN/Asystem.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses 37610726SN/Asystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 37710726SN/Asystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 37810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses 37910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses 38010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 38110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 38210726SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 38310726SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 38410726SN/Asystem.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 38510726SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 38610726SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 38710726SN/Asystem.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses 38810726SN/Asystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency 38910726SN/Asystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency 39010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadCleanReq miss latency 39110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.139005 # average ReadCleanReq miss latency 39210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency 39310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency 39410726SN/Asystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency 39510726SN/Asystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency 39610726SN/Asystem.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency 39710726SN/Asystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency 39810726SN/Asystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency 39910726SN/Asystem.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency 40010726SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 40110726SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 40210726SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 40310726SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 40410726SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 40510726SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 40610726SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 40710726SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 40810726SN/Asystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 40910726SN/Asystem.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 41010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses 41110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses 41210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses 41310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses 41410726SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 41510726SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 41610726SN/Asystem.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 41710726SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 41810726SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 41910726SN/Asystem.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses 42010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45815000 # number of ReadExReq MSHR miss cycles 42110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45815000 # number of ReadExReq MSHR miss cycles 42210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 152873000 # number of ReadCleanReq MSHR miss cycles 42310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 152873000 # number of ReadCleanReq MSHR miss cycles 42410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 21165000 # number of ReadSharedReq MSHR miss cycles 42510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 21165000 # number of ReadSharedReq MSHR miss cycles 42610892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 152873000 # number of demand (read+write) MSHR miss cycles 42710892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66980000 # number of demand (read+write) MSHR miss cycles 42810892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 219853000 # number of demand (read+write) MSHR miss cycles 42910892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 152873000 # number of overall MSHR miss cycles 43010892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66980000 # number of overall MSHR miss cycles 43110892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 219853000 # number of overall MSHR miss cycles 43210726SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 43310726SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 43410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses 43510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses 43610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 43710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 43810726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 43910726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 44010726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 44110726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 44210726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 44310726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses 44410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency 44510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency 44610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.139005 # average ReadCleanReq mshr miss latency 44710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.139005 # average ReadCleanReq mshr miss latency 44810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency 44910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 45010892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency 45110892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 45210892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency 45310892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency 45410892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 45510892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency 45610726SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 4579729SN/Asystem.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 4589729SN/Asystem.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution 45910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 10362 # Transaction distribution 4609729SN/Asystem.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 4619729SN/Asystem.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 46210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 46310892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 46410892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) 4659838SN/Asystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 46610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) 46710409SN/Asystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) 46810409SN/Asystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 46910409SN/Asystem.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) 47010409SN/Asystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 47110892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 24228 # Request fanout histogram 47210409SN/Asystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 47310409SN/Asystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 47410409SN/Asystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 47510409SN/Asystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 47610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 24228 100.00% 100.00% # Request fanout histogram 47710409SN/Asystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 47810409SN/Asystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 47910409SN/Asystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 48010409SN/Asystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 48110892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 24228 # Request fanout histogram 48210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 12116000 # Layer occupancy (ticks) 4839729SN/Asystem.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 4849729SN/Asystem.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 4859729SN/Asystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 4869729SN/Asystem.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 4879729SN/Asystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 48810726SN/Asystem.membus.trans_dist::ReadResp 4095 # Transaction distribution 48910726SN/Asystem.membus.trans_dist::ReadExReq 1078 # Transaction distribution 49010726SN/Asystem.membus.trans_dist::ReadExResp 1078 # Transaction distribution 49110892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution 49210726SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 49310726SN/Asystem.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 49410726SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 49510726SN/Asystem.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) 49610726SN/Asystem.membus.snoops 0 # Total snoops (count) 49710726SN/Asystem.membus.snoop_fanout::samples 5173 # Request fanout histogram 49810726SN/Asystem.membus.snoop_fanout::mean 0 # Request fanout histogram 49910726SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 50010726SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 50110726SN/Asystem.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram 50210726SN/Asystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 50310726SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 50410726SN/Asystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 50510726SN/Asystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 50610726SN/Asystem.membus.snoop_fanout::total 5173 # Request fanout histogram 50710726SN/Asystem.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks) 50810726SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 50910726SN/Asystem.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks) 51010726SN/Asystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 5114312SN/A 5124312SN/A---------- End Simulation Statistics ---------- 513