stats.txt revision 10488
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270563 # Number of seconds simulated 4sim_ticks 270563082000 # Number of ticks simulated 5final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1449498 # Simulator instruction rate (inst/s) 8host_op_rate 1449499 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2027353723 # Simulator tick rate (ticks/s) 10host_mem_usage 294428 # Number of bytes of host memory used 11host_seconds 133.46 # Real time elapsed on the host 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 18system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) 32system.membus.trans_dist::ReadReq 4095 # Transaction distribution 33system.membus.trans_dist::ReadResp 4095 # Transaction distribution 34system.membus.trans_dist::ReadExReq 1078 # Transaction distribution 35system.membus.trans_dist::ReadExResp 1078 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 5173 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 5173 # Request fanout histogram 51system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 53system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.workload.num_syscalls 401 # Number of system calls 57system.cpu.numCycles 541126164 # number of cpu cycles simulated 58system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 59system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 60system.cpu.committedInsts 193444518 # Number of instructions committed 61system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 62system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 63system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 64system.cpu.num_func_calls 1957920 # number of times a function call or return occured 65system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 66system.cpu.num_int_insts 167974806 # number of integer instructions 67system.cpu.num_fp_insts 1970372 # number of float instructions 68system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 69system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 70system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 71system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 72system.cpu.num_mem_refs 76733958 # number of memory refs 73system.cpu.num_load_insts 57735091 # Number of load instructions 74system.cpu.num_store_insts 18998867 # Number of store instructions 75system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 76system.cpu.num_busy_cycles 541126163.998000 # Number of busy cycles 77system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 78system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 79system.cpu.Branches 15132745 # Number of branches fetched 80system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 81system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 82system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 83system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 84system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction 85system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction 86system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction 87system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction 88system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction 89system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction 90system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction 91system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction 92system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction 93system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction 94system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction 95system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction 96system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction 97system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction 98system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction 99system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction 100system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction 101system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction 102system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction 103system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction 104system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction 105system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction 106system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction 107system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 109system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 110system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 111system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 112system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 113system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 114system.cpu.op_class::total 193445773 # Class of executed instruction 115system.cpu.icache.tags.replacements 10362 # number of replacements 116system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use 117system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 118system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 119system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 120system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 121system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor 122system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy 123system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy 124system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 125system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 126system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 127system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 128system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 129system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 130system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 131system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 132system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses 133system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 134system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 135system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 136system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 137system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 138system.cpu.icache.overall_hits::total 193433248 # number of overall hits 139system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 140system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 141system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 142system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 143system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 144system.cpu.icache.overall_misses::total 12288 # number of overall misses 145system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles 146system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles 147system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles 148system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles 149system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles 150system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles 151system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 152system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 153system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 154system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 155system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 156system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 157system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 158system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 159system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 160system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 161system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 162system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses 163system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency 164system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency 165system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency 166system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency 167system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency 168system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency 169system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175system.cpu.icache.fast_writes 0 # number of fast writes performed 176system.cpu.icache.cache_copies 0 # number of cache copies performed 177system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 178system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 179system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 180system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 181system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 182system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses 183system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles 184system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles 185system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles 186system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles 187system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles 188system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles 189system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 190system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 191system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 192system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 193system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 194system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 195system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency 196system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency 197system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency 198system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency 199system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency 200system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency 201system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 202system.cpu.l2cache.tags.replacements 0 # number of replacements 203system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use 204system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. 205system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 206system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. 207system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 208system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor 209system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor 210system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor 211system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 212system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy 213system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 214system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy 215system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id 216system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 217system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id 218system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id 219system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id 220system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id 221system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id 222system.cpu.l2cache.tags.tag_accesses 116103 # Number of tag accesses 223system.cpu.l2cache.tags.data_accesses 116103 # Number of data accesses 224system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits 225system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits 226system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits 227system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits 228system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 229system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits 230system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits 231system.cpu.l2cache.overall_hits::total 8691 # number of overall hits 232system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses 233system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 234system.cpu.l2cache.ReadReq_misses::total 4095 # number of ReadReq misses 235system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses 236system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses 237system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 238system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 239system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 240system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 241system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 242system.cpu.l2cache.overall_misses::total 5173 # number of overall misses 243system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187044000 # number of ReadReq miss cycles 244system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25896000 # number of ReadReq miss cycles 245system.cpu.l2cache.ReadReq_miss_latency::total 212940000 # number of ReadReq miss cycles 246system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56056000 # number of ReadExReq miss cycles 247system.cpu.l2cache.ReadExReq_miss_latency::total 56056000 # number of ReadExReq miss cycles 248system.cpu.l2cache.demand_miss_latency::cpu.inst 187044000 # number of demand (read+write) miss cycles 249system.cpu.l2cache.demand_miss_latency::cpu.data 81952000 # number of demand (read+write) miss cycles 250system.cpu.l2cache.demand_miss_latency::total 268996000 # number of demand (read+write) miss cycles 251system.cpu.l2cache.overall_miss_latency::cpu.inst 187044000 # number of overall miss cycles 252system.cpu.l2cache.overall_miss_latency::cpu.data 81952000 # number of overall miss cycles 253system.cpu.l2cache.overall_miss_latency::total 268996000 # number of overall miss cycles 254system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) 255system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) 256system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) 257system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) 258system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) 259system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 260system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 261system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses 262system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses 263system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses 264system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses 265system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses 266system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses 267system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses 268system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 269system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses 270system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 271system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 272system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 273system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 274system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 275system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 276system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 277system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses 278system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 279system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 280system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 281system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 282system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 283system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 284system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 285system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 286system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 287system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 288system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 289system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 290system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 291system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 292system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 293system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 294system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 295system.cpu.l2cache.fast_writes 0 # number of fast writes performed 296system.cpu.l2cache.cache_copies 0 # number of cache copies performed 297system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses 298system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 299system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses 300system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 301system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 302system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 303system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 304system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 305system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 306system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 307system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses 308system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles 309system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles 310system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles 311system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles 312system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles 313system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles 314system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles 315system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles 316system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles 317system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles 318system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles 319system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses 320system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 321system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses 322system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 323system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 324system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 325system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 326system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 327system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 328system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 329system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses 330system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 331system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 332system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 333system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 334system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 335system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 336system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 337system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 338system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 339system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 340system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 341system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 342system.cpu.dcache.tags.replacements 2 # number of replacements 343system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use 344system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 345system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 346system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 347system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 348system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor 349system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy 350system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy 351system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 352system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 353system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 354system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 355system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 356system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 357system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 358system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 359system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses 360system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 361system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 362system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 363system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 364system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 365system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 366system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 367system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits 368system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits 369system.cpu.dcache.overall_hits::total 76709932 # number of overall hits 370system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 371system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses 372system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 373system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 374system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 375system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 376system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 377system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 378system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 379system.cpu.dcache.overall_misses::total 1575 # number of overall misses 380system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles 381system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles 382system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles 383system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles 384system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles 385system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles 386system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles 387system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles 388system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles 389system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles 390system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 391system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 393system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 395system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 396system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 397system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses 398system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses 399system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses 400system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses 401system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses 402system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 403system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 404system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 405system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 406system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 407system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 408system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 409system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses 410system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 411system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 412system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 413system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 414system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency 415system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency 416system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 417system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 418system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 419system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 420system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 421system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 422system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 425system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 426system.cpu.dcache.fast_writes 0 # number of fast writes performed 427system.cpu.dcache.cache_copies 0 # number of cache copies performed 428system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 429system.cpu.dcache.writebacks::total 2 # number of writebacks 430system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 431system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 432system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 433system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 434system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 435system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 436system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 437system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 438system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 439system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses 440system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles 441system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles 442system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles 443system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles 444system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles 445system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles 446system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles 447system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles 448system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles 449system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles 450system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 451system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 452system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 453system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 454system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 455system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 456system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 457system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 458system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 459system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses 460system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 461system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 462system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 463system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 464system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency 465system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency 466system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 467system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 468system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 469system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 470system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 471system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 476system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 478system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes) 479system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) 480system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 481system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) 482system.cpu.toL2Bus.snoops 0 # Total snoops (count) 483system.cpu.toL2Bus.snoop_fanout::samples 13866 # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 487system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::1 13866 100.00% 100.00% # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::total 13866 # Request fanout histogram 494system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks) 495system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 496system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 497system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 498system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 499system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 500 501---------- End Simulation Statistics ---------- 502